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-rw-r--r--arch/mips/include/asm/mips-boards/generic.h40
1 files changed, 20 insertions, 20 deletions
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index c01e286394da..1465b1193b12 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -27,39 +27,39 @@
27/* 27/*
28 * Display register base. 28 * Display register base.
29 */ 29 */
30#define ASCII_DISPLAY_WORD_BASE 0x1f000410 30#define ASCII_DISPLAY_WORD_BASE 0x1f000410
31#define ASCII_DISPLAY_POS_BASE 0x1f000418 31#define ASCII_DISPLAY_POS_BASE 0x1f000418
32 32
33 33
34/* 34/*
35 * Yamon Prom print address. 35 * Yamon Prom print address.
36 */ 36 */
37#define YAMON_PROM_PRINT_ADDR 0x1fc00504 37#define YAMON_PROM_PRINT_ADDR 0x1fc00504
38 38
39 39
40/* 40/*
41 * Reset register. 41 * Reset register.
42 */ 42 */
43#define SOFTRES_REG 0x1f000500 43#define SOFTRES_REG 0x1f000500
44#define GORESET 0x42 44#define GORESET 0x42
45 45
46/* 46/*
47 * Revision register. 47 * Revision register.
48 */ 48 */
49#define MIPS_REVISION_REG 0x1fc00010 49#define MIPS_REVISION_REG 0x1fc00010
50#define MIPS_REVISION_CORID_QED_RM5261 0 50#define MIPS_REVISION_CORID_QED_RM5261 0
51#define MIPS_REVISION_CORID_CORE_LV 1 51#define MIPS_REVISION_CORID_CORE_LV 1
52#define MIPS_REVISION_CORID_BONITO64 2 52#define MIPS_REVISION_CORID_BONITO64 2
53#define MIPS_REVISION_CORID_CORE_20K 3 53#define MIPS_REVISION_CORID_CORE_20K 3
54#define MIPS_REVISION_CORID_CORE_FPGA 4 54#define MIPS_REVISION_CORID_CORE_FPGA 4
55#define MIPS_REVISION_CORID_CORE_MSC 5 55#define MIPS_REVISION_CORID_CORE_MSC 5
56#define MIPS_REVISION_CORID_CORE_EMUL 6 56#define MIPS_REVISION_CORID_CORE_EMUL 6
57#define MIPS_REVISION_CORID_CORE_FPGA2 7 57#define MIPS_REVISION_CORID_CORE_FPGA2 7
58#define MIPS_REVISION_CORID_CORE_FPGAR2 8 58#define MIPS_REVISION_CORID_CORE_FPGAR2 8
59#define MIPS_REVISION_CORID_CORE_FPGA3 9 59#define MIPS_REVISION_CORID_CORE_FPGA3 9
60#define MIPS_REVISION_CORID_CORE_24K 10 60#define MIPS_REVISION_CORID_CORE_24K 10
61#define MIPS_REVISION_CORID_CORE_FPGA4 11 61#define MIPS_REVISION_CORID_CORE_FPGA4 11
62#define MIPS_REVISION_CORID_CORE_FPGA5 12 62#define MIPS_REVISION_CORID_CORE_FPGA5 12
63 63
64/**** Artificial corid defines ****/ 64/**** Artificial corid defines ****/
65/* 65/*
@@ -97,4 +97,4 @@ extern void mips_pcibios_init(void);
97#define mips_pcibios_init() do { } while (0) 97#define mips_pcibios_init() do { } while (0)
98#endif 98#endif
99 99
100#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 100#endif /* __ASM_MIPS_BOARDS_GENERIC_H */