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-rw-r--r--arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h81
-rw-r--r--arch/mips/include/asm/mach-rc32434/ddr.h141
-rw-r--r--arch/mips/include/asm/mach-rc32434/dma.h103
-rw-r--r--arch/mips/include/asm/mach-rc32434/dma_v.h52
-rw-r--r--arch/mips/include/asm/mach-rc32434/eth.h220
-rw-r--r--arch/mips/include/asm/mach-rc32434/gpio.h88
-rw-r--r--arch/mips/include/asm/mach-rc32434/integ.h59
-rw-r--r--arch/mips/include/asm/mach-rc32434/irq.h33
-rw-r--r--arch/mips/include/asm/mach-rc32434/pci.h481
-rw-r--r--arch/mips/include/asm/mach-rc32434/prom.h40
-rw-r--r--arch/mips/include/asm/mach-rc32434/rb.h84
-rw-r--r--arch/mips/include/asm/mach-rc32434/rc32434.h19
-rw-r--r--arch/mips/include/asm/mach-rc32434/timer.h65
-rw-r--r--arch/mips/include/asm/mach-rc32434/war.h25
14 files changed, 1491 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f3bc7efa2608
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
@@ -0,0 +1,81 @@
1/*
2 * IDT RC32434 specific CPU feature overrides
3 *
4 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
5 *
6 * This file was derived from: include/asm-mips/cpu-features.h
7 * Copyright (C) 2003, 2004 Ralf Baechle
8 * Copyright (C) 2004 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the
22 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
23 * Boston, MA 02110-1301, USA.
24 */
25#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
26#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
27
28/*
29 * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
30 */
31#define cpu_has_tlb 1
32#define cpu_has_4kex 1
33#define cpu_has_3k_cache 0
34#define cpu_has_4k_cache 1
35#define cpu_has_tx39_cache 0
36#define cpu_has_sb1_cache 0
37#define cpu_has_fpu 0
38#define cpu_has_32fpr 0
39#define cpu_has_counter 1
40#define cpu_has_watch 1
41#define cpu_has_divec 1
42#define cpu_has_vce 0
43#define cpu_has_cache_cdex_p 0
44#define cpu_has_cache_cdex_s 0
45#define cpu_has_prefetch 1
46#define cpu_has_mcheck 1
47#define cpu_has_ejtag 1
48#define cpu_has_llsc 1
49
50#define cpu_has_mips16 0
51#define cpu_has_mdmx 0
52#define cpu_has_mips3d 0
53#define cpu_has_smartmips 0
54
55#define cpu_has_vtag_icache 0
56/* #define cpu_has_dc_aliases ? */
57/* #define cpu_has_ic_fills_f_dc ? */
58/* #define cpu_has_pindexed_dcache ? */
59
60/* #define cpu_icache_snoops_remote_store ? */
61
62#define cpu_has_mips32r1 1
63#define cpu_has_mips32r2 0
64#define cpu_has_mips64r1 0
65#define cpu_has_mips64r2 0
66
67#define cpu_has_dsp 0
68#define cpu_has_mipsmt 0
69
70/* #define cpu_has_nofpuex ? */
71#define cpu_has_64bits 0
72#define cpu_has_64bit_zero_reg 0
73#define cpu_has_64bit_gp_regs 0
74#define cpu_has_64bit_addresses 0
75
76#define cpu_has_inclusive_pcaches 0
77
78#define cpu_dcache_line_size() 16
79#define cpu_icache_line_size() 16
80
81#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-rc32434/ddr.h b/arch/mips/include/asm/mach-rc32434/ddr.h
new file mode 100644
index 000000000000..291e2cf9dde0
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/ddr.h
@@ -0,0 +1,141 @@
1/*
2 * Definitions for the DDR registers
3 *
4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef _ASM_RC32434_DDR_H_
30#define _ASM_RC32434_DDR_H_
31
32#include <asm/mach-rc32434/rb.h>
33
34/* DDR register structure */
35struct ddr_ram {
36 u32 ddrbase;
37 u32 ddrmask;
38 u32 res1;
39 u32 res2;
40 u32 ddrc;
41 u32 ddrabase;
42 u32 ddramask;
43 u32 ddramap;
44 u32 ddrcust;
45 u32 ddrrdc;
46 u32 ddrspare;
47};
48
49#define DDR0_PHYS_ADDR 0x18018000
50
51/* DDR banks masks */
52#define DDR_MASK 0xffff0000
53#define DDR0_BASE_MSK DDR_MASK
54#define DDR1_BASE_MSK DDR_MASK
55
56/* DDR bank0 registers */
57#define RC32434_DDR0_ATA_BIT 5
58#define RC32434_DDR0_ATA_MSK 0x000000E0
59#define RC32434_DDR0_DBW_BIT 8
60#define RC32434_DDR0_DBW_MSK 0x00000100
61#define RC32434_DDR0_WR_BIT 9
62#define RC32434_DDR0_WR_MSK 0x00000600
63#define RC32434_DDR0_PS_BIT 11
64#define RC32434_DDR0_PS_MSK 0x00001800
65#define RC32434_DDR0_DTYPE_BIT 13
66#define RC32434_DDR0_DTYPE_MSK 0x0000e000
67#define RC32434_DDR0_RFC_BIT 16
68#define RC32434_DDR0_RFC_MSK 0x000f0000
69#define RC32434_DDR0_RP_BIT 20
70#define RC32434_DDR0_RP_MSK 0x00300000
71#define RC32434_DDR0_AP_BIT 22
72#define RC32434_DDR0_AP_MSK 0x00400000
73#define RC32434_DDR0_RCD_BIT 23
74#define RC32434_DDR0_RCD_MSK 0x01800000
75#define RC32434_DDR0_CL_BIT 25
76#define RC32434_DDR0_CL_MSK 0x06000000
77#define RC32434_DDR0_DBM_BIT 27
78#define RC32434_DDR0_DBM_MSK 0x08000000
79#define RC32434_DDR0_SDS_BIT 28
80#define RC32434_DDR0_SDS_MSK 0x10000000
81#define RC32434_DDR0_ATP_BIT 29
82#define RC32434_DDR0_ATP_MSK 0x60000000
83#define RC32434_DDR0_RE_BIT 31
84#define RC32434_DDR0_RE_MSK 0x80000000
85
86/* DDR bank C registers */
87#define RC32434_DDRC_MSK(x) BIT_TO_MASK(x)
88#define RC32434_DDRC_CES_BIT 0
89#define RC32434_DDRC_ACE_BIT 1
90
91/* Custom DDR bank registers */
92#define RC32434_DCST_MSK(x) BIT_TO_MASK(x)
93#define RC32434_DCST_CS_BIT 0
94#define RC32434_DCST_CS_MSK 0x00000003
95#define RC32434_DCST_WE_BIT 2
96#define RC32434_DCST_RAS_BIT 3
97#define RC32434_DCST_CAS_BIT 4
98#define RC32434_DSCT_CKE_BIT 5
99#define RC32434_DSCT_BA_BIT 6
100#define RC32434_DSCT_BA_MSK 0x000000c0
101
102/* DDR QSC registers */
103#define RC32434_QSC_DM_BIT 0
104#define RC32434_QSC_DM_MSK 0x00000003
105#define RC32434_QSC_DQSBS_BIT 2
106#define RC32434_QSC_DQSBS_MSK 0x000000fc
107#define RC32434_QSC_DB_BIT 8
108#define RC32434_QSC_DB_MSK 0x00000100
109#define RC32434_QSC_DBSP_BIT 9
110#define RC32434_QSC_DBSP_MSK 0x01fffe00
111#define RC32434_QSC_BDP_BIT 25
112#define RC32434_QSC_BDP_MSK 0x7e000000
113
114/* DDR LLC registers */
115#define RC32434_LLC_EAO_BIT 0
116#define RC32434_LLC_EAO_MSK 0x00000001
117#define RC32434_LLC_EO_BIT 1
118#define RC32434_LLC_EO_MSK 0x0000003e
119#define RC32434_LLC_FS_BIT 6
120#define RC32434_LLC_FS_MSK 0x000000c0
121#define RC32434_LLC_AS_BIT 8
122#define RC32434_LLC_AS_MSK 0x00000700
123#define RC32434_LLC_SP_BIT 11
124#define RC32434_LLC_SP_MSK 0x001ff800
125
126/* DDR LLFC registers */
127#define RC32434_LLFC_MSK(x) BIT_TO_MASK(x)
128#define RC32434_LLFC_MEN_BIT 0
129#define RC32434_LLFC_EAN_BIT 1
130#define RC32434_LLFC_FF_BIT 2
131
132/* DDR DLLTA registers */
133#define RC32434_DLLTA_ADDR_BIT 2
134#define RC32434_DLLTA_ADDR_MSK 0xfffffffc
135
136/* DDR DLLED registers */
137#define RC32434_DLLED_MSK(x) BIT_TO_MASK(x)
138#define RC32434_DLLED_DBE_BIT 0
139#define RC32434_DLLED_DTE_BIT 1
140
141#endif /* _ASM_RC32434_DDR_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/dma.h b/arch/mips/include/asm/mach-rc32434/dma.h
new file mode 100644
index 000000000000..5f898b5873f7
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/dma.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * DMA register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 */
10
11#ifndef __ASM_RC32434_DMA_H
12#define __ASM_RC32434_DMA_H
13
14#include <asm/mach-rc32434/rb.h>
15
16#define DMA0_BASE_ADDR 0x18040000
17
18/*
19 * DMA descriptor (in physical memory).
20 */
21
22struct dma_desc {
23 u32 control; /* Control. use DMAD_* */
24 u32 ca; /* Current Address. */
25 u32 devcs; /* Device control and status. */
26 u32 link; /* Next descriptor in chain. */
27};
28
29#define DMA_DESC_SIZ sizeof(struct dma_desc)
30#define DMA_DESC_COUNT_BIT 0
31#define DMA_DESC_COUNT_MSK 0x0003ffff
32#define DMA_DESC_DS_BIT 20
33#define DMA_DESC_DS_MSK 0x00300000
34
35#define DMA_DESC_DEV_CMD_BIT 22
36#define DMA_DESC_DEV_CMD_MSK 0x01c00000
37
38/* DMA command sizes */
39#define DMA_DESC_DEV_CMD_BYTE 0
40#define DMA_DESC_DEV_CMD_HLF_WD 1
41#define DMA_DESC_DEV_CMD_WORD 2
42#define DMA_DESC_DEV_CMD_2WORDS 3
43#define DMA_DESC_DEV_CMD_4WORDS 4
44#define DMA_DESC_DEV_CMD_6WORDS 5
45#define DMA_DESC_DEV_CMD_8WORDS 6
46#define DMA_DESC_DEV_CMD_16WORDS 7
47
48/* DMA descriptors interrupts */
49#define DMA_DESC_COF (1 << 25) /* Chain on finished */
50#define DMA_DESC_COD (1 << 26) /* Chain on done */
51#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */
52#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */
53#define DMA_DESC_TERM (1 << 29) /* Terminated */
54#define DMA_DESC_DONE (1 << 30) /* Done */
55#define DMA_DESC_FINI (1 << 31) /* Finished */
56
57/*
58 * DMA register (within Internal Register Map).
59 */
60
61struct dma_reg {
62 u32 dmac; /* Control. */
63 u32 dmas; /* Status. */
64 u32 dmasm; /* Mask. */
65 u32 dmadptr; /* Descriptor pointer. */
66 u32 dmandptr; /* Next descriptor pointer. */
67};
68
69/* DMA channels specific registers */
70#define DMA_CHAN_RUN_BIT (1 << 0)
71#define DMA_CHAN_DONE_BIT (1 << 1)
72#define DMA_CHAN_MODE_BIT (1 << 2)
73#define DMA_CHAN_MODE_MSK 0x0000000c
74#define DMA_CHAN_MODE_AUTO 0
75#define DMA_CHAN_MODE_BURST 1
76#define DMA_CHAN_MODE_XFRT 2
77#define DMA_CHAN_MODE_RSVD 3
78#define DMA_CHAN_ACT_BIT (1 << 4)
79
80/* DMA status registers */
81#define DMA_STAT_FINI (1 << 0)
82#define DMA_STAT_DONE (1 << 1)
83#define DMA_STAT_CHAIN (1 << 2)
84#define DMA_STAT_ERR (1 << 3)
85#define DMA_STAT_HALT (1 << 4)
86
87/*
88 * DMA channel definitions
89 */
90
91#define DMA_CHAN_ETH_RCV 0
92#define DMA_CHAN_ETH_XMT 1
93#define DMA_CHAN_MEM_TO_FIFO 2
94#define DMA_CHAN_FIFO_TO_MEM 3
95#define DMA_CHAN_PCI_TO_MEM 4
96#define DMA_CHAN_MEM_TO_PCI 5
97#define DMA_CHAN_COUNT 6
98
99struct dma_channel {
100 struct dma_reg ch[DMA_CHAN_COUNT];
101};
102
103#endif /* __ASM_RC32434_DMA_H */
diff --git a/arch/mips/include/asm/mach-rc32434/dma_v.h b/arch/mips/include/asm/mach-rc32434/dma_v.h
new file mode 100644
index 000000000000..173a9f9146cd
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/dma_v.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * DMA register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 */
10
11#ifndef _ASM_RC32434_DMA_V_H_
12#define _ASM_RC32434_DMA_V_H_
13
14#include <asm/mach-rc32434/dma.h>
15#include <asm/mach-rc32434/rc32434.h>
16
17#define DMA_CHAN_OFFSET 0x14
18#define IS_DMA_USED(X) (((X) & \
19 (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
20 != 0)
21#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK)
22
23#define DMA_HALT_TIMEOUT 500
24
25static inline int rc32434_halt_dma(struct dma_reg *ch)
26{
27 int timeout = 1;
28 if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
29 __raw_writel(0, &ch->dmac);
30 for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
31 if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
32 __raw_writel(0, &ch->dmas);
33 break;
34 }
35 }
36 }
37
38 return timeout ? 0 : 1;
39}
40
41static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
42{
43 __raw_writel(0, &ch->dmandptr);
44 __raw_writel(dma_addr, &ch->dmadptr);
45}
46
47static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
48{
49 __raw_writel(dma_addr, &ch->dmandptr);
50}
51
52#endif /* _ASM_RC32434_DMA_V_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/eth.h b/arch/mips/include/asm/mach-rc32434/eth.h
new file mode 100644
index 000000000000..a25cbc56173d
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/eth.h
@@ -0,0 +1,220 @@
1/*
2 * Definitions for the Ethernet registers
3 *
4 * Copyright 2002 Allend Stichter <allen.stichter@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef __ASM_RC32434_ETH_H
30#define __ASM_RC32434_ETH_H
31
32
33#define ETH0_BASE_ADDR 0x18060000
34
35struct eth_regs {
36 u32 ethintfc;
37 u32 ethfifott;
38 u32 etharc;
39 u32 ethhash0;
40 u32 ethhash1;
41 u32 ethu0[4]; /* Reserved. */
42 u32 ethpfs;
43 u32 ethmcp;
44 u32 eth_u1[10]; /* Reserved. */
45 u32 ethspare;
46 u32 eth_u2[42]; /* Reserved. */
47 u32 ethsal0;
48 u32 ethsah0;
49 u32 ethsal1;
50 u32 ethsah1;
51 u32 ethsal2;
52 u32 ethsah2;
53 u32 ethsal3;
54 u32 ethsah3;
55 u32 ethrbc;
56 u32 ethrpc;
57 u32 ethrupc;
58 u32 ethrfc;
59 u32 ethtbc;
60 u32 ethgpf;
61 u32 eth_u9[50]; /* Reserved. */
62 u32 ethmac1;
63 u32 ethmac2;
64 u32 ethipgt;
65 u32 ethipgr;
66 u32 ethclrt;
67 u32 ethmaxf;
68 u32 eth_u10; /* Reserved. */
69 u32 ethmtest;
70 u32 miimcfg;
71 u32 miimcmd;
72 u32 miimaddr;
73 u32 miimwtd;
74 u32 miimrdd;
75 u32 miimind;
76 u32 eth_u11; /* Reserved. */
77 u32 eth_u12; /* Reserved. */
78 u32 ethcfsa0;
79 u32 ethcfsa1;
80 u32 ethcfsa2;
81};
82
83/* Ethernet interrupt registers */
84#define ETH_INT_FC_EN (1 << 0)
85#define ETH_INT_FC_ITS (1 << 1)
86#define ETH_INT_FC_RIP (1 << 2)
87#define ETH_INT_FC_JAM (1 << 3)
88#define ETH_INT_FC_OVR (1 << 4)
89#define ETH_INT_FC_UND (1 << 5)
90#define ETH_INT_FC_IOC 0x000000c0
91
92/* Ethernet FIFO registers */
93#define ETH_FIFI_TT_TTH_BIT 0
94#define ETH_FIFO_TT_TTH 0x0000007f
95
96/* Ethernet ARC/multicast registers */
97#define ETH_ARC_PRO (1 << 0)
98#define ETH_ARC_AM (1 << 1)
99#define ETH_ARC_AFM (1 << 2)
100#define ETH_ARC_AB (1 << 3)
101
102/* Ethernet SAL registers */
103#define ETH_SAL_BYTE_5 0x000000ff
104#define ETH_SAL_BYTE_4 0x0000ff00
105#define ETH_SAL_BYTE_3 0x00ff0000
106#define ETH_SAL_BYTE_2 0xff000000
107
108/* Ethernet SAH registers */
109#define ETH_SAH_BYTE1 0x000000ff
110#define ETH_SAH_BYTE0 0x0000ff00
111
112/* Ethernet GPF register */
113#define ETH_GPF_PTV 0x0000ffff
114
115/* Ethernet PFG register */
116#define ETH_PFS_PFD (1 << 0)
117
118/* Ethernet CFSA[0-3] registers */
119#define ETH_CFSA0_CFSA4 0x000000ff
120#define ETH_CFSA0_CFSA5 0x0000ff00
121#define ETH_CFSA1_CFSA2 0x000000ff
122#define ETH_CFSA1_CFSA3 0x0000ff00
123#define ETH_CFSA1_CFSA0 0x000000ff
124#define ETH_CFSA1_CFSA1 0x0000ff00
125
126/* Ethernet MAC1 registers */
127#define ETH_MAC1_RE (1 << 0)
128#define ETH_MAC1_PAF (1 << 1)
129#define ETH_MAC1_RFC (1 << 2)
130#define ETH_MAC1_TFC (1 << 3)
131#define ETH_MAC1_LB (1 << 4)
132#define ETH_MAC1_MR (1 << 31)
133
134/* Ethernet MAC2 registers */
135#define ETH_MAC2_FD (1 << 0)
136#define ETH_MAC2_FLC (1 << 1)
137#define ETH_MAC2_HFE (1 << 2)
138#define ETH_MAC2_DC (1 << 3)
139#define ETH_MAC2_CEN (1 << 4)
140#define ETH_MAC2_PE (1 << 5)
141#define ETH_MAC2_VPE (1 << 6)
142#define ETH_MAC2_APE (1 << 7)
143#define ETH_MAC2_PPE (1 << 8)
144#define ETH_MAC2_LPE (1 << 9)
145#define ETH_MAC2_NB (1 << 12)
146#define ETH_MAC2_BP (1 << 13)
147#define ETH_MAC2_ED (1 << 14)
148
149/* Ethernet IPGT register */
150#define ETH_IPGT 0x0000007f
151
152/* Ethernet IPGR registers */
153#define ETH_IPGR_IPGR2 0x0000007f
154#define ETH_IPGR_IPGR1 0x00007f00
155
156/* Ethernet CLRT registers */
157#define ETH_CLRT_MAX_RET 0x0000000f
158#define ETH_CLRT_COL_WIN 0x00003f00
159
160/* Ethernet MAXF register */
161#define ETH_MAXF 0x0000ffff
162
163/* Ethernet test registers */
164#define ETH_TEST_REG (1 << 2)
165#define ETH_MCP_DIV 0x000000ff
166
167/* MII registers */
168#define ETH_MII_CFG_RSVD 0x0000000c
169#define ETH_MII_CMD_RD (1 << 0)
170#define ETH_MII_CMD_SCN (1 << 1)
171#define ETH_MII_REG_ADDR 0x0000001f
172#define ETH_MII_PHY_ADDR 0x00001f00
173#define ETH_MII_WTD_DATA 0x0000ffff
174#define ETH_MII_RDD_DATA 0x0000ffff
175#define ETH_MII_IND_BSY (1 << 0)
176#define ETH_MII_IND_SCN (1 << 1)
177#define ETH_MII_IND_NV (1 << 2)
178
179/*
180 * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
181 */
182
183#define ETH_RX_FD (1 << 0)
184#define ETH_RX_LD (1 << 1)
185#define ETH_RX_ROK (1 << 2)
186#define ETH_RX_FM (1 << 3)
187#define ETH_RX_MP (1 << 4)
188#define ETH_RX_BP (1 << 5)
189#define ETH_RX_VLT (1 << 6)
190#define ETH_RX_CF (1 << 7)
191#define ETH_RX_OVR (1 << 8)
192#define ETH_RX_CRC (1 << 9)
193#define ETH_RX_CV (1 << 10)
194#define ETH_RX_DB (1 << 11)
195#define ETH_RX_LE (1 << 12)
196#define ETH_RX_LOR (1 << 13)
197#define ETH_RX_CES (1 << 14)
198#define ETH_RX_LEN_BIT 16
199#define ETH_RX_LEN 0xffff0000
200
201#define ETH_TX_FD (1 << 0)
202#define ETH_TX_LD (1 << 1)
203#define ETH_TX_OEN (1 << 2)
204#define ETH_TX_PEN (1 << 3)
205#define ETH_TX_CEN (1 << 4)
206#define ETH_TX_HEN (1 << 5)
207#define ETH_TX_TOK (1 << 6)
208#define ETH_TX_MP (1 << 7)
209#define ETH_TX_BP (1 << 8)
210#define ETH_TX_UND (1 << 9)
211#define ETH_TX_OF (1 << 10)
212#define ETH_TX_ED (1 << 11)
213#define ETH_TX_EC (1 << 12)
214#define ETH_TX_LC (1 << 13)
215#define ETH_TX_TD (1 << 14)
216#define ETH_TX_CRC (1 << 15)
217#define ETH_TX_LE (1 << 16)
218#define ETH_TX_CC 0x001E0000
219
220#endif /* __ASM_RC32434_ETH_H */
diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
new file mode 100644
index 000000000000..3a70b41cd7a5
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -0,0 +1,88 @@
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * GPIO register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
10 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
11 */
12
13#ifndef _RC32434_GPIO_H_
14#define _RC32434_GPIO_H_
15
16#include <linux/types.h>
17
18#define gpio_get_value __gpio_get_value
19#define gpio_set_value __gpio_set_value
20
21#define gpio_cansleep __gpio_cansleep
22
23#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
24#define irq_to_gpio(irq) IRQ_TO_GPIO(irq)
25
26#include <asm-generic/gpio.h>
27
28struct rb532_gpio_reg {
29 u32 gpiofunc; /* GPIO Function Register
30 * gpiofunc[x]==0 bit = gpio
31 * func[x]==1 bit = altfunc
32 */
33 u32 gpiocfg; /* GPIO Configuration Register
34 * gpiocfg[x]==0 bit = input
35 * gpiocfg[x]==1 bit = output
36 */
37 u32 gpiod; /* GPIO Data Register
38 * gpiod[x] read/write gpio pinX status
39 */
40 u32 gpioilevel; /* GPIO Interrupt Status Register
41 * interrupt level (see gpioistat)
42 */
43 u32 gpioistat; /* Gpio Interrupt Status Register
44 * istat[x] = (gpiod[x] == level[x])
45 * cleared in ISR (STICKY bits)
46 */
47 u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
48};
49
50/* UART GPIO signals */
51#define RC32434_UART0_SOUT (1 << 0)
52#define RC32434_UART0_SIN (1 << 1)
53#define RC32434_UART0_RTS (1 << 2)
54#define RC32434_UART0_CTS (1 << 3)
55
56/* M & P bus GPIO signals */
57#define RC32434_MP_BIT_22 (1 << 4)
58#define RC32434_MP_BIT_23 (1 << 5)
59#define RC32434_MP_BIT_24 (1 << 6)
60#define RC32434_MP_BIT_25 (1 << 7)
61
62/* CPU GPIO signals */
63#define RC32434_CPU_GPIO (1 << 8)
64
65/* Reserved GPIO signals */
66#define RC32434_AF_SPARE_6 (1 << 9)
67#define RC32434_AF_SPARE_4 (1 << 10)
68#define RC32434_AF_SPARE_3 (1 << 11)
69#define RC32434_AF_SPARE_2 (1 << 12)
70
71/* PCI messaging unit */
72#define RC32434_PCI_MSU_GPIO (1 << 13)
73
74/* NAND GPIO signals */
75#define GPIO_RDY 8
76#define GPIO_WPX 9
77#define GPIO_ALE 10
78#define GPIO_CLE 11
79
80/* Compact Flash GPIO pin */
81#define CF_GPIO_NUM 13
82
83extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
84extern unsigned get_434_reg(unsigned reg_offs);
85extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
86extern unsigned char get_latch_u5(void);
87
88#endif /* _RC32434_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/integ.h b/arch/mips/include/asm/mach-rc32434/integ.h
new file mode 100644
index 000000000000..fa65bc3d8807
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/integ.h
@@ -0,0 +1,59 @@
1/*
2 * Definitions for the Watchdog registers
3 *
4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef __RC32434_INTEG_H__
30#define __RC32434_INTEG_H__
31
32#include <asm/mach-rc32434/rb.h>
33
34#define INTEG0_BASE_ADDR 0x18030030
35
36struct integ {
37 u32 errcs; /* sticky use ERRCS_ */
38 u32 wtcount; /* Watchdog timer count reg. */
39 u32 wtcompare; /* Watchdog timer timeout value. */
40 u32 wtc; /* Watchdog timer control. use WTC_ */
41};
42
43/* Error counters */
44#define RC32434_ERR_WTO 0
45#define RC32434_ERR_WNE 1
46#define RC32434_ERR_UCW 2
47#define RC32434_ERR_UCR 3
48#define RC32434_ERR_UPW 4
49#define RC32434_ERR_UPR 5
50#define RC32434_ERR_UDW 6
51#define RC32434_ERR_UDR 7
52#define RC32434_ERR_SAE 8
53#define RC32434_ERR_WRE 9
54
55/* Watchdog control bits */
56#define RC32434_WTC_EN 0
57#define RC32434_WTC_TO 1
58
59#endif /* __RC32434_INTEG_H__ */
diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h
new file mode 100644
index 000000000000..56738d8ec4e2
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/irq.h
@@ -0,0 +1,33 @@
1#ifndef __ASM_RC32434_IRQ_H
2#define __ASM_RC32434_IRQ_H
3
4#define NR_IRQS 256
5
6#include <asm/mach-generic/irq.h>
7#include <asm/mach-rc32434/rb.h>
8
9/* Interrupt Controller */
10#define IC_GROUP0_PEND (REGBASE + 0x38000)
11#define IC_GROUP0_MASK (REGBASE + 0x38008)
12#define IC_GROUP_OFFSET 0x0C
13
14#define NUM_INTR_GROUPS 5
15
16/* 16550 UARTs */
17#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
18 /* GRP3 IRQ numbers start here */
19#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
20 /* GRP4 IRQ numbers start here */
21#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
22 /* GRP5 IRQ numbers start here */
23#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
24#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
25
26#define UART0_IRQ (GROUP3_IRQ_BASE + 0)
27
28#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
29#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
30#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
31#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
32
33#endif /* __ASM_RC32434_IRQ_H */
diff --git a/arch/mips/include/asm/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h
new file mode 100644
index 000000000000..410638f2af74
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/pci.h
@@ -0,0 +1,481 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2004 IDT Inc. (rischelp@idt.com)
23 *
24 * Initial Release
25 */
26
27#ifndef _ASM_RC32434_PCI_H_
28#define _ASM_RC32434_PCI_H_
29
30#define epld_mask ((volatile unsigned char *)0xB900000d)
31
32#define PCI0_BASE_ADDR 0x18080000
33#define PCI_LBA_COUNT 4
34
35struct pci_map {
36 u32 address; /* Address. */
37 u32 control; /* Control. */
38 u32 mapping; /* mapping. */
39};
40
41struct pci_reg {
42 u32 pcic;
43 u32 pcis;
44 u32 pcism;
45 u32 pcicfga;
46 u32 pcicfgd;
47 volatile struct pci_map pcilba[PCI_LBA_COUNT];
48 u32 pcidac;
49 u32 pcidas;
50 u32 pcidasm;
51 u32 pcidad;
52 u32 pcidma8c;
53 u32 pcidma9c;
54 u32 pcitc;
55};
56
57#define PCI_MSU_COUNT 2
58
59struct pci_msu {
60 u32 pciim[PCI_MSU_COUNT];
61 u32 pciom[PCI_MSU_COUNT];
62 u32 pciid;
63 u32 pciiic;
64 u32 pciiim;
65 u32 pciiod;
66 u32 pciioic;
67 u32 pciioim;
68};
69
70/*
71 * PCI Control Register
72 */
73
74#define PCI_CTL_EN (1 << 0)
75#define PCI_CTL_TNR (1 << 1)
76#define PCI_CTL_SCE (1 << 2)
77#define PCI_CTL_IEN (1 << 3)
78#define PCI_CTL_AAA (1 << 4)
79#define PCI_CTL_EAP (1 << 5)
80#define PCI_CTL_PCIM_BIT 6
81#define PCI_CTL_PCIM 0x000001c0
82
83#define PCI_CTL_PCIM_DIS 0
84#define PCI_CTL_PCIM_TNR 1 /* Satellite - target not ready */
85#define PCI_CTL_PCIM_SUS 2 /* Satellite - suspended CPU. */
86#define PCI_CTL_PCIM_EXT 3 /* Host - external arbiter. */
87#define PCI_CTL PCIM_PRIO 4 /* Host - fixed priority arb. */
88#define PCI_CTL_PCIM_RR 5 /* Host - round robin priority. */
89#define PCI_CTL_PCIM_RSVD6 6
90#define PCI_CTL_PCIM_RSVD7 7
91
92#define PCI_CTL_IGM (1 << 9)
93
94/*
95 * PCI Status Register
96 */
97
98#define PCI_STAT_EED (1 << 0)
99#define PCI_STAT_WR (1 << 1)
100#define PCI_STAT_NMI (1 << 2)
101#define PCI_STAT_II (1 << 3)
102#define PCI_STAT_CWE (1 << 4)
103#define PCI_STAT_CRE (1 << 5)
104#define PCI_STAT_MDPE (1 << 6)
105#define PCI_STAT_STA (1 << 7)
106#define PCI_STAT_RTA (1 << 8)
107#define PCI_STAT_RMA (1 << 9)
108#define PCI_STAT_SSE (1 << 10)
109#define PCI_STAT_OSE (1 << 11)
110#define PCI_STAT_PE (1 << 12)
111#define PCI_STAT_TAE (1 << 13)
112#define PCI_STAT_RLE (1 << 14)
113#define PCI_STAT_BME (1 << 15)
114#define PCI_STAT_PRD (1 << 16)
115#define PCI_STAT_RIP (1 << 17)
116
117/*
118 * PCI Status Mask Register
119 */
120
121#define PCI_STATM_EED PCI_STAT_EED
122#define PCI_STATM_WR PCI_STAT_WR
123#define PCI_STATM_NMI PCI_STAT_NMI
124#define PCI_STATM_II PCI_STAT_II
125#define PCI_STATM_CWE PCI_STAT_CWE
126#define PCI_STATM_CRE PCI_STAT_CRE
127#define PCI_STATM_MDPE PCI_STAT_MDPE
128#define PCI_STATM_STA PCI_STAT_STA
129#define PCI_STATM_RTA PCI_STAT_RTA
130#define PCI_STATM_RMA PCI_STAT_RMA
131#define PCI_STATM_SSE PCI_STAT_SSE
132#define PCI_STATM_OSE PCI_STAT_OSE
133#define PCI_STATM_PE PCI_STAT_PE
134#define PCI_STATM_TAE PCI_STAT_TAE
135#define PCI_STATM_RLE PCI_STAT_RLE
136#define PCI_STATM_BME PCI_STAT_BME
137#define PCI_STATM_PRD PCI_STAT_PRD
138#define PCI_STATM_RIP PCI_STAT_RIP
139
140/*
141 * PCI Configuration Address Register
142 */
143#define PCI_CFGA_REG_BIT 2
144#define PCI_CFGA_REG 0x000000fc
145#define PCI_CFGA_REG_ID (0x00 >> 2) /* use PCFGID */
146#define PCI_CFGA_REG_04 (0x04 >> 2) /* use PCFG04_ */
147#define PCI_CFGA_REG_08 (0x08 >> 2) /* use PCFG08_ */
148#define PCI_CFGA_REG_0C (0x0C >> 2) /* use PCFG0C_ */
149#define PCI_CFGA_REG_PBA0 (0x10 >> 2) /* use PCIPBA_ */
150#define PCI_CFGA_REG_PBA1 (0x14 >> 2) /* use PCIPBA_ */
151#define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */
152#define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */
153#define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */
154#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */
155#define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */
156#define PCI_CFGA_REG_PBA0M (0x48 >> 2)
157#define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */
158#define PCI_CFGA_REG_PBA1M (0x50 >> 2)
159#define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */
160#define PCI_CFGA_REG_PBA2M (0x58 >> 2)
161#define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */
162#define PCI_CFGA_REG_PBA3M (0x60 >> 2)
163#define PCI_CFGA_REG_PMGT (0x64 >> 2)
164#define PCI_CFGA_FUNC_BIT 8
165#define PCI_CFGA_FUNC 0x00000700
166#define PCI_CFGA_DEV_BIT 11
167#define PCI_CFGA_DEV 0x0000f800
168#define PCI_CFGA_DEV_INTERN 0
169#define PCI_CFGA_BUS_BIT 16
170#define PCI CFGA_BUS 0x00ff0000
171#define PCI_CFGA_BUS_TYPE0 0
172#define PCI_CFGA_EN (1 << 31)
173
174/* PCI CFG04 commands */
175#define PCI_CFG04_CMD_IO_ENA (1 << 0)
176#define PCI_CFG04_CMD_MEM_ENA (1 << 1)
177#define PCI_CFG04_CMD_BM_ENA (1 << 2)
178#define PCI_CFG04_CMD_MW_INV (1 << 4)
179#define PCI_CFG04_CMD_PAR_ENA (1 << 6)
180#define PCI_CFG04_CMD_SER_ENA (1 << 8)
181#define PCI_CFG04_CMD_FAST_ENA (1 << 9)
182
183/* PCI CFG04 status fields */
184#define PCI_CFG04_STAT_BIT 16
185#define PCI_CFG04_STAT 0xffff0000
186#define PCI_CFG04_STAT_66_MHZ (1 << 21)
187#define PCI_CFG04_STAT_FBB (1 << 23)
188#define PCI_CFG04_STAT_MDPE (1 << 24)
189#define PCI_CFG04_STAT_DST (1 << 25)
190#define PCI_CFG04_STAT_STA (1 << 27)
191#define PCI_CFG04_STAT_RTA (1 << 28)
192#define PCI_CFG04_STAT_RMA (1 << 29)
193#define PCI_CFG04_STAT_SSE (1 << 30)
194#define PCI_CFG04_STAT_PE (1 << 31)
195
196#define PCI_PBA_MSI (1 << 0)
197#define PCI_PBA_P (1 << 2)
198
199/* PCI PBAC registers */
200#define PCI_PBAC_MSI (1 << 0)
201#define PCI_PBAC_P (1 << 1)
202#define PCI_PBAC_SIZE_BIT 2
203#define PCI_PBAC_SIZE 0x0000007c
204#define PCI_PBAC_SB (1 << 7)
205#define PCI_PBAC_PP (1 << 8)
206#define PCI_PBAC_MR_BIT 9
207#define PCI_PBAC_MR 0x00000600
208#define PCI_PBAC_MR_RD 0
209#define PCI_PBAC_MR_RD_LINE 1
210#define PCI_PBAC_MR_RD_MULT 2
211#define PCI_PBAC_MRL (1 << 11)
212#define PCI_PBAC_MRM (1 << 12)
213#define PCI_PBAC_TRP (1 << 13)
214
215#define PCI_CFG40_TRDY_TIM 0x000000ff
216#define PCI_CFG40_RET_LIM 0x0000ff00
217
218/*
219 * PCI Local Base Address [0|1|2|3] Register
220 */
221
222#define PCI_LBA_BADDR_BIT 0
223#define PCI_LBA_BADDR 0xffffff00
224
225/*
226 * PCI Local Base Address Control Register
227 */
228
229#define PCI_LBAC_MSI (1 << 0)
230#define PCI_LBAC_MSI_MEM 0
231#define PCI_LBAC_MSI_IO 1
232#define PCI_LBAC_SIZE_BIT 2
233#define PCI_LBAC_SIZE 0x0000007c
234#define PCI_LBAC_SB (1 << 7)
235#define PCI_LBAC_RT (1 << 8)
236#define PCI_LBAC_RT_NO_PREF 0
237#define PCI_LBAC_RT_PREF 1
238
239/*
240 * PCI Local Base Address [0|1|2|3] Mapping Register
241 */
242#define PCI_LBAM_MADDR_BIT 8
243#define PCI_LBAM_MADDR 0xffffff00
244
245/*
246 * PCI Decoupled Access Control Register
247 */
248#define PCI_DAC_DEN (1 << 0)
249
250/*
251 * PCI Decoupled Access Status Register
252 */
253#define PCI_DAS_D (1 << 0)
254#define PCI_DAS_B (1 << 1)
255#define PCI_DAS_E (1 << 2)
256#define PCI_DAS_OFE (1 << 3)
257#define PCI_DAS_OFF (1 << 4)
258#define PCI_DAS_IFE (1 << 5)
259#define PCI_DAS_IFF (1 << 6)
260
261/*
262 * PCI DMA Channel 8 Configuration Register
263 */
264#define PCI_DMA8C_MBS_BIT 0
265#define PCI_DMA8C_MBS 0x00000fff /* Maximum Burst Size. */
266#define PCI_DMA8C_OUR (1 << 12)
267
268/*
269 * PCI DMA Channel 9 Configuration Register
270 */
271#define PCI_DMA9C_MBS_BIT 0 /* Maximum Burst Size. */
272#define PCI_DMA9C_MBS 0x00000fff
273
274/*
275 * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
276 */
277
278#define PCI_DMAD_PT_BIT 22 /* in DEVCMD field (descriptor) */
279#define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */
280/* These are for reads (DMA channel 8) */
281#define PCI_DMAD_DEVCMD_MR 0 /* memory read */
282#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */
283#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */
284#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */
285/* These are for writes (DMA channel 9) */
286#define PCI_DMAD_DEVCMD_MW 0 /* memory write */
287#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */
288#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */
289
290/* Swap byte field applies to both DMA channel 8 and 9 */
291#define PCI_DMAD_SB (1 << 24) /* swap byte field */
292
293
294/*
295 * PCI Target Control Register
296 */
297
298#define PCI_TC_RTIMER_BIT 0
299#define PCI_TC_RTIMER 0x000000ff
300#define PCI_TC_DTIMER_BIT 8
301#define PCI_TC_DTIMER 0x0000ff00
302#define PCI_TC_RDR (1 << 18)
303#define PCI_TC_DDT (1 << 19)
304
305/*
306 * PCI messaging unit [applies to both inbound and outbound registers ]
307 */
308#define PCI_MSU_M0 (1 << 0)
309#define PCI_MSU_M1 (1 << 1)
310#define PCI_MSU_DB (1 << 2)
311
312#define PCI_MSG_ADDR 0xB8088010
313#define PCI0_ADDR 0xB8080000
314#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
315#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
316
317#define PCIM_SHFT 0x6
318#define PCIM_BIT_LEN 0x7
319#define PCIM_H_EA 0x3
320#define PCIM_H_IA_FIX 0x4
321#define PCIM_H_IA_RR 0x5
322#if 0
323#define PCI_ADDR_START 0x13000000
324#endif
325
326#define PCI_ADDR_START 0x50000000
327
328#define CPUTOPCI_MEM_WIN 0x02000000
329#define CPUTOPCI_IO_WIN 0x00100000
330#define PCILBA_SIZE_SHFT 2
331#define PCILBA_SIZE_MASK 0x1F
332#define SIZE_256MB 0x1C
333#define SIZE_128MB 0x1B
334#define SIZE_64MB 0x1A
335#define SIZE_32MB 0x19
336#define SIZE_16MB 0x18
337#define SIZE_4MB 0x16
338#define SIZE_2MB 0x15
339#define SIZE_1MB 0x14
340#define KORINA_CONFIG0_ADDR 0x80000000
341#define KORINA_CONFIG1_ADDR 0x80000004
342#define KORINA_CONFIG2_ADDR 0x80000008
343#define KORINA_CONFIG3_ADDR 0x8000000C
344#define KORINA_CONFIG4_ADDR 0x80000010
345#define KORINA_CONFIG5_ADDR 0x80000014
346#define KORINA_CONFIG6_ADDR 0x80000018
347#define KORINA_CONFIG7_ADDR 0x8000001C
348#define KORINA_CONFIG8_ADDR 0x80000020
349#define KORINA_CONFIG9_ADDR 0x80000024
350#define KORINA_CONFIG10_ADDR 0x80000028
351#define KORINA_CONFIG11_ADDR 0x8000002C
352#define KORINA_CONFIG12_ADDR 0x80000030
353#define KORINA_CONFIG13_ADDR 0x80000034
354#define KORINA_CONFIG14_ADDR 0x80000038
355#define KORINA_CONFIG15_ADDR 0x8000003C
356#define KORINA_CONFIG16_ADDR 0x80000040
357#define KORINA_CONFIG17_ADDR 0x80000044
358#define KORINA_CONFIG18_ADDR 0x80000048
359#define KORINA_CONFIG19_ADDR 0x8000004C
360#define KORINA_CONFIG20_ADDR 0x80000050
361#define KORINA_CONFIG21_ADDR 0x80000054
362#define KORINA_CONFIG22_ADDR 0x80000058
363#define KORINA_CONFIG23_ADDR 0x8000005C
364#define KORINA_CONFIG24_ADDR 0x80000060
365#define KORINA_CONFIG25_ADDR 0x80000064
366#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \
367 PCI_CFG04_CMD_MEM_ENA | \
368 PCI_CFG04_CMD_BM_ENA | \
369 PCI_CFG04_CMD_MW_INV | \
370 PCI_CFG04_CMD_PAR_ENA | \
371 PCI_CFG04_CMD_SER_ENA)
372
373#define KORINA_STAT (PCI_CFG04_STAT_MDPE | \
374 PCI_CFG04_STAT_STA | \
375 PCI_CFG04_STAT_RTA | \
376 PCI_CFG04_STAT_RMA | \
377 PCI_CFG04_STAT_SSE | \
378 PCI_CFG04_STAT_PE)
379
380#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
381
382#define KORINA_REVID 0
383#define KORINA_CLASS_CODE 0
384#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
385 KORINA_REVID)
386
387#define KORINA_CACHE_LINE_SIZE 4
388#define KORINA_MASTER_LAT 0x3c
389#define KORINA_HEADER_TYPE 0
390#define KORINA_BIST 0
391
392#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
393 (KORINA_HEADER_TYPE<<16) | \
394 (KORINA_MASTER_LAT<<8) | \
395 KORINA_CACHE_LINE_SIZE)
396
397#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
398#define KORINA_BAR1 0x18800001 /* 1 MB IO */
399#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
400 internal Registers */
401#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
402
403#define KORINA_CNFG4 KORINA_BAR0
404#define KORINA_CNFG5 KORINA_BAR1
405#define KORINA_CNFG6 KORINA_BAR2
406#define KORINA_CNFG7 KORINA_BAR3
407
408#define KORINA_SUBSYS_VENDOR_ID 0x011d
409#define KORINA_SUBSYSTEM_ID 0x0214
410#define KORINA_CNFG8 0
411#define KORINA_CNFG9 0
412#define KORINA_CNFG10 0
413#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
414 KORINA_SUBSYSTEM_ID)
415#define KORINA_INT_LINE 1
416#define KORINA_INT_PIN 1
417#define KORINA_MIN_GNT 8
418#define KORINA_MAX_LAT 0x38
419#define KORINA_CNFG12 0
420#define KORINA_CNFG13 0
421#define KORINA_CNFG14 0
422#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
423 (KORINA_MIN_GNT<<16) | \
424 (KORINA_INT_PIN<<8) | \
425 KORINA_INT_LINE)
426#define KORINA_RETRY_LIMIT 0x80
427#define KORINA_TRDY_LIMIT 0x80
428#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
429 KORINA_TRDY_LIMIT)
430#define PCI_PBAxC_R 0x0
431#define PCI_PBAxC_RL 0x1
432#define PCI_PBAxC_RM 0x2
433#define SIZE_SHFT 2
434
435#if defined(__MIPSEB__)
436#define KORINA_PBA0C (PCI_PBAC_MRL | PCI_PBAC_SB | \
437 ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
438 PCI_PBAC_PP | \
439 (SIZE_128MB<<SIZE_SHFT) | \
440 PCI_PBAC_P)
441#else
442#define KORINA_PBA0C (PCI_PBAC_MRL | \
443 ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
444 PCI_PBAC_PP | \
445 (SIZE_128MB<<SIZE_SHFT) | \
446 PCI_PBAC_P)
447#endif
448#define KORINA_CNFG17 KORINA_PBA0C
449#define KORINA_PBA0M 0x0
450#define KORINA_CNFG18 KORINA_PBA0M
451
452#if defined(__MIPSEB__)
453#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
454 PCI_PBAC_MSI)
455#else
456#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
457 PCI_PBAC_MSI)
458#endif
459#define KORINA_CNFG19 KORINA_PBA1C
460#define KORINA_PBA1M 0x0
461#define KORINA_CNFG20 KORINA_PBA1M
462
463#if defined(__MIPSEB__)
464#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
465 PCI_PBAC_MSI)
466#else
467#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
468 PCI_PBAC_MSI)
469#endif
470#define KORINA_CNFG21 KORINA_PBA2C
471#define KORINA_PBA2M 0x18000000
472#define KORINA_CNFG22 KORINA_PBA2M
473#define KORINA_PBA3C 0
474#define KORINA_CNFG23 KORINA_PBA3C
475#define KORINA_PBA3M 0
476#define KORINA_CNFG24 KORINA_PBA3M
477
478#define PCITC_DTIMER_VAL 8
479#define PCITC_RTIMER_VAL 0x10
480
481#endif /* __ASM_RC32434_PCI_H */
diff --git a/arch/mips/include/asm/mach-rc32434/prom.h b/arch/mips/include/asm/mach-rc32434/prom.h
new file mode 100644
index 000000000000..660707f1bcce
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/prom.h
@@ -0,0 +1,40 @@
1/*
2 * Definitions for the PROM
3 *
4 * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8))
30
31#define SR_NMI 0x00180000
32#define SERIAL_SPEED_ENTRY 0x00000001
33
34#define FREQ_TAG "HZ="
35#define KMAC_TAG "kmac="
36#define MEM_TAG "mem="
37#define BOARD_TAG "board="
38
39#define BOARD_RB532 "500"
40#define BOARD_RB532A "500r5"
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
new file mode 100644
index 000000000000..79e8ef67d0d3
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -0,0 +1,84 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * Copyright (C) 2004 IDT Inc.
13 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
14 */
15#ifndef __ASM_RC32434_RB_H
16#define __ASM_RC32434_RB_H
17
18#include <linux/genhd.h>
19
20#define REGBASE 0x18000000
21#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
22#define UART0BASE 0x58000
23#define RST (1 << 15)
24#define DEV0BASE 0x010000
25#define DEV0MASK 0x010004
26#define DEV0C 0x010008
27#define DEV0T 0x01000C
28#define DEV1BASE 0x010010
29#define DEV1MASK 0x010014
30#define DEV1C 0x010018
31#define DEV1TC 0x01001C
32#define DEV2BASE 0x010020
33#define DEV2MASK 0x010024
34#define DEV2C 0x010028
35#define DEV2TC 0x01002C
36#define DEV3BASE 0x010030
37#define DEV3MASK 0x010034
38#define DEV3C 0x010038
39#define DEV3TC 0x01003C
40#define BTCS 0x010040
41#define BTCOMPARE 0x010044
42#define GPIOBASE 0x050000
43#define GPIOCFG 0x050004
44#define GPIOD 0x050008
45#define GPIOILEVEL 0x05000C
46#define GPIOISTAT 0x050010
47#define GPIONMIEN 0x050014
48#define IMASK6 0x038038
49#define LO_WPX (1 << 0)
50#define LO_ALE (1 << 1)
51#define LO_CLE (1 << 2)
52#define LO_CEX (1 << 3)
53#define LO_FOFF (1 << 5)
54#define LO_SPICS (1 << 6)
55#define LO_ULED (1 << 7)
56
57#define BIT_TO_MASK(x) (1 << x)
58
59struct dev_reg {
60 u32 base;
61 u32 mask;
62 u32 ctl;
63 u32 timing;
64};
65
66struct korina_device {
67 char *name;
68 unsigned char mac[6];
69 struct net_device *dev;
70};
71
72struct cf_device {
73 int gpio_pin;
74 void *dev;
75 struct gendisk *gd;
76};
77
78struct mpmc_device {
79 unsigned char state;
80 spinlock_t lock;
81 void __iomem *base;
82};
83
84#endif /* __ASM_RC32434_RB_H */
diff --git a/arch/mips/include/asm/mach-rc32434/rc32434.h b/arch/mips/include/asm/mach-rc32434/rc32434.h
new file mode 100644
index 000000000000..fce25d4231fc
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/rc32434.h
@@ -0,0 +1,19 @@
1/*
2 * Definitions for IDT RC323434 CPU.
3 */
4
5#ifndef _ASM_RC32434_RC32434_H_
6#define _ASM_RC32434_RC32434_H_
7
8#include <linux/delay.h>
9#include <linux/io.h>
10
11#define IDT_CLOCK_MULT 2
12
13/* cpu pipeline flush */
14static inline void rc32434_sync(void)
15{
16 __asm__ volatile ("sync");
17}
18
19#endif /* _ASM_RC32434_RC32434_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/timer.h b/arch/mips/include/asm/mach-rc32434/timer.h
new file mode 100644
index 000000000000..e49b1d57a017
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/timer.h
@@ -0,0 +1,65 @@
1/*
2 * Definitions for timer registers
3 *
4 * Copyright 2004 Philip Rischel <rischelp@idt.com>
5 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28
29#ifndef __ASM_RC32434_TIMER_H
30#define __ASM_RC32434_TIMER_H
31
32#include <asm/mach-rc32434/rb.h>
33
34#define TIMER0_BASE_ADDR 0x18028000
35#define TIMER_COUNT 3
36
37struct timer_counter {
38 u32 count;
39 u32 compare;
40 u32 ctc; /*use CTC_ */
41};
42
43struct timer {
44 struct timer_counter tim[TIMER_COUNT];
45 u32 rcount; /* use RCOUNT_ */
46 u32 rcompare; /* use RCOMPARE_ */
47 u32 rtc; /* use RTC_ */
48};
49
50#define RC32434_CTC_EN_BIT 0
51#define RC32434_CTC_TO_BIT 1
52
53/* Real time clock registers */
54#define RC32434_RTC_MSK(x) BIT_TO_MASK(x)
55#define RC32434_RTC_CE_BIT 0
56#define RC32434_RTC_TO_BIT 1
57#define RC32434_RTC_RQE_BIT 2
58
59/* Counter registers */
60#define RC32434_RCOUNT_BIT 0
61#define RC32434_RCOUNT_MSK 0x0000ffff
62#define RC32434_RCOMP_BIT 0
63#define RC32434_RCOMP_MSK 0x0000ffff
64
65#endif /* __ASM_RC32434_TIMER_H */
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
new file mode 100644
index 000000000000..3ddf187e98a6
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
9#define __ASM_MIPS_MACH_MIPS_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 13:36:57 -0500