3 files changed, 203 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
new file mode 100644
index 000000000000..5a508f9f9432
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -0,0 +1,39 @@
+/*
+ *  Ralink SoC register definitions
+ *
+ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _RALINK_REGS_H_
+#define _RALINK_REGS_H_
+
+extern __iomem void *rt_sysc_membase;
+extern __iomem void *rt_memc_membase;
+
+static inline void rt_sysc_w32(u32 val, unsigned reg)
+{
+        __raw_writel(val, rt_sysc_membase + reg);
+}
+
+static inline u32 rt_sysc_r32(unsigned reg)
+{
+        return __raw_readl(rt_sysc_membase + reg);
+}
+
+static inline void rt_memc_w32(u32 val, unsigned reg)
+{
+        __raw_writel(val, rt_memc_membase + reg);
+}
+
+static inline u32 rt_memc_r32(unsigned reg)
+{
+        return __raw_readl(rt_memc_membase + reg);
+}
+
+#endif /* _RALINK_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
new file mode 100644
index 000000000000..7d344f2d7d0a
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -0,0 +1,139 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _RT305X_REGS_H_
+#define _RT305X_REGS_H_
+
+enum rt305x_soc_type {
+        RT305X_SOC_UNKNOWN = 0,
+        RT305X_SOC_RT3050,
+        RT305X_SOC_RT3052,
+        RT305X_SOC_RT3350,
+        RT305X_SOC_RT3352,
+        RT305X_SOC_RT5350,
+};
+
+extern enum rt305x_soc_type rt305x_soc;
+
+static inline int soc_is_rt3050(void)
+{
+        return rt305x_soc == RT305X_SOC_RT3050;
+}
+
+static inline int soc_is_rt3052(void)
+{
+        return rt305x_soc == RT305X_SOC_RT3052;
+}
+
+static inline int soc_is_rt305x(void)
+{
+        return soc_is_rt3050() || soc_is_rt3052();
+}
+
+static inline int soc_is_rt3350(void)
+{
+        return rt305x_soc == RT305X_SOC_RT3350;
+}
+
+static inline int soc_is_rt3352(void)
+{
+        return rt305x_soc == RT305X_SOC_RT3352;
+}
+
+static inline int soc_is_rt5350(void)
+{
+        return rt305x_soc == RT305X_SOC_RT5350;
+}
+
+#define RT305X_SYSC_BASE                0x10000000
+
+#define SYSC_REG_CHIP_NAME0             0x00
+#define SYSC_REG_CHIP_NAME1             0x04
+#define SYSC_REG_CHIP_ID                0x0c
+#define SYSC_REG_SYSTEM_CONFIG          0x10
+
+#define RT3052_CHIP_NAME0               0x30335452
+#define RT3052_CHIP_NAME1               0x20203235
+
+#define RT3350_CHIP_NAME0               0x33335452
+#define RT3350_CHIP_NAME1               0x20203035
+
+#define RT3352_CHIP_NAME0               0x33335452
+#define RT3352_CHIP_NAME1               0x20203235
+
+#define RT5350_CHIP_NAME0               0x33355452
+#define RT5350_CHIP_NAME1               0x20203035
+
+#define CHIP_ID_ID_MASK                 0xff
+#define CHIP_ID_ID_SHIFT                8
+#define CHIP_ID_REV_MASK                0xff
+
+#define RT305X_SYSCFG_CPUCLK_SHIFT              18
+#define RT305X_SYSCFG_CPUCLK_MASK               0x1
+#define RT305X_SYSCFG_CPUCLK_LOW                0x0
+#define RT305X_SYSCFG_CPUCLK_HIGH               0x1
+
+#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT       2
+#define RT305X_SYSCFG_CPUCLK_MASK               0x1
+#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT         0x1
+
+#define RT3352_SYSCFG0_CPUCLK_SHIFT     8
+#define RT3352_SYSCFG0_CPUCLK_MASK      0x1
+#define RT3352_SYSCFG0_CPUCLK_LOW       0x0
+#define RT3352_SYSCFG0_CPUCLK_HIGH      0x1
+
+#define RT5350_SYSCFG0_CPUCLK_SHIFT     8
+#define RT5350_SYSCFG0_CPUCLK_MASK      0x3
+#define RT5350_SYSCFG0_CPUCLK_360       0x0
+#define RT5350_SYSCFG0_CPUCLK_320       0x2
+#define RT5350_SYSCFG0_CPUCLK_300       0x3
+
+/* multi function gpio pins */
+#define RT305X_GPIO_I2C_SD              1
+#define RT305X_GPIO_I2C_SCLK            2
+#define RT305X_GPIO_SPI_EN              3
+#define RT305X_GPIO_SPI_CLK             4
+/* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
+#define RT305X_GPIO_7                   7
+#define RT305X_GPIO_10                  10
+#define RT305X_GPIO_14                  14
+#define RT305X_GPIO_UART1_TXD           15
+#define RT305X_GPIO_UART1_RXD           16
+#define RT305X_GPIO_JTAG_TDO            17
+#define RT305X_GPIO_JTAG_TDI            18
+#define RT305X_GPIO_MDIO_MDC            22
+#define RT305X_GPIO_MDIO_MDIO           23
+#define RT305X_GPIO_SDRAM_MD16          24
+#define RT305X_GPIO_SDRAM_MD31          39
+#define RT305X_GPIO_GE0_TXD0            40
+#define RT305X_GPIO_GE0_RXCLK           51
+
+#define RT305X_GPIO_MODE_I2C            BIT(0)
+#define RT305X_GPIO_MODE_SPI            BIT(1)
+#define RT305X_GPIO_MODE_UART0_SHIFT    2
+#define RT305X_GPIO_MODE_UART0_MASK     0x7
+#define RT305X_GPIO_MODE_UART0(x)       ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
+#define RT305X_GPIO_MODE_UARTF          0x0
+#define RT305X_GPIO_MODE_PCM_UARTF      0x1
+#define RT305X_GPIO_MODE_PCM_I2S        0x2
+#define RT305X_GPIO_MODE_I2S_UARTF      0x3
+#define RT305X_GPIO_MODE_PCM_GPIO       0x4
+#define RT305X_GPIO_MODE_GPIO_UARTF     0x5
+#define RT305X_GPIO_MODE_GPIO_I2S       0x6
+#define RT305X_GPIO_MODE_GPIO           0x7
+#define RT305X_GPIO_MODE_UART1          BIT(5)
+#define RT305X_GPIO_MODE_JTAG           BIT(6)
+#define RT305X_GPIO_MODE_MDIO           BIT(7)
+#define RT305X_GPIO_MODE_SDRAM          BIT(8)
+#define RT305X_GPIO_MODE_RGMII          BIT(9)
+
+#endif
diff --git a/arch/mips/include/asm/mach-ralink/war.h b/arch/mips/include/asm/mach-ralink/war.h
new file mode 100644
index 000000000000..a7b712cf2d28
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_RALINK_WAR_H
+#define __ASM_MACH_RALINK_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MACH_RALINK_WAR_H */