1 files changed, 20 insertions, 15 deletions

diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index 069bf37a6010..96f731bac79a 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -125,24 +125,29 @@ static inline int soc_is_rt5350(void)
 #define RT305X_GPIO_GE0_TXD0            40
 #define RT305X_GPIO_GE0_RXCLK           51
 
-#define RT305X_GPIO_MODE_I2C            BIT(0)
-#define RT305X_GPIO_MODE_SPI            BIT(1)
 #define RT305X_GPIO_MODE_UART0_SHIFT    2
 #define RT305X_GPIO_MODE_UART0_MASK     0x7
 #define RT305X_GPIO_MODE_UART0(x)       ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
-#define RT305X_GPIO_MODE_UARTF          0x0
-#define RT305X_GPIO_MODE_PCM_UARTF      0x1
-#define RT305X_GPIO_MODE_PCM_I2S        0x2
-#define RT305X_GPIO_MODE_I2S_UARTF      0x3
-#define RT305X_GPIO_MODE_PCM_GPIO       0x4
-#define RT305X_GPIO_MODE_GPIO_UARTF     0x5
-#define RT305X_GPIO_MODE_GPIO_I2S       0x6
-#define RT305X_GPIO_MODE_GPIO           0x7
-#define RT305X_GPIO_MODE_UART1          BIT(5)
-#define RT305X_GPIO_MODE_JTAG           BIT(6)
-#define RT305X_GPIO_MODE_MDIO           BIT(7)
-#define RT305X_GPIO_MODE_SDRAM          BIT(8)
-#define RT305X_GPIO_MODE_RGMII          BIT(9)
+#define RT305X_GPIO_MODE_UARTF          0
+#define RT305X_GPIO_MODE_PCM_UARTF      1
+#define RT305X_GPIO_MODE_PCM_I2S        2
+#define RT305X_GPIO_MODE_I2S_UARTF      3
+#define RT305X_GPIO_MODE_PCM_GPIO       4
+#define RT305X_GPIO_MODE_GPIO_UARTF     5
+#define RT305X_GPIO_MODE_GPIO_I2S       6
+#define RT305X_GPIO_MODE_GPIO           7
+
+#define RT305X_GPIO_MODE_I2C            0
+#define RT305X_GPIO_MODE_SPI            1
+#define RT305X_GPIO_MODE_UART1          5
+#define RT305X_GPIO_MODE_JTAG           6
+#define RT305X_GPIO_MODE_MDIO           7
+#define RT305X_GPIO_MODE_SDRAM          8
+#define RT305X_GPIO_MODE_RGMII          9
+#define RT5350_GPIO_MODE_PHY_LED        14
+#define RT5350_GPIO_MODE_SPI_CS1        21
+#define RT3352_GPIO_MODE_LNA            18
+#define RT3352_GPIO_MODE_PA             20
 
 #define RT3352_SYSC_REG_SYSCFG0         0x010
 #define RT3352_SYSC_REG_SYSCFG1         0x014