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-rw-r--r--arch/mips/include/asm/mach-malta/cpu-feature-overrides.h72
-rw-r--r--arch/mips/include/asm/mach-malta/irq.h9
-rw-r--r--arch/mips/include/asm/mach-malta/kernel-entry-init.h52
-rw-r--r--arch/mips/include/asm/mach-malta/mach-gt64120.h19
-rw-r--r--arch/mips/include/asm/mach-malta/mc146818rtc.h48
-rw-r--r--arch/mips/include/asm/mach-malta/war.h25
6 files changed, 225 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
new file mode 100644
index 000000000000..7f3e3f9bd23a
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
@@ -0,0 +1,72 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Chris Dearman
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8 */
9#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
11
12
13/*
14 * CPU feature overrides for MIPS boards
15 */
16#ifdef CONFIG_CPU_MIPS32
17#define cpu_has_tlb 1
18#define cpu_has_4kex 1
19#define cpu_has_4k_cache 1
20/* #define cpu_has_fpu ? */
21/* #define cpu_has_32fpr ? */
22#define cpu_has_counter 1
23/* #define cpu_has_watch ? */
24#define cpu_has_divec 1
25#define cpu_has_vce 0
26/* #define cpu_has_cache_cdex_p ? */
27/* #define cpu_has_cache_cdex_s ? */
28/* #define cpu_has_prefetch ? */
29#define cpu_has_mcheck 1
30/* #define cpu_has_ejtag ? */
31#ifdef CONFIG_CPU_HAS_LLSC
32#define cpu_has_llsc 1
33#else
34#define cpu_has_llsc 0
35#endif
36/* #define cpu_has_vtag_icache ? */
37/* #define cpu_has_dc_aliases ? */
38/* #define cpu_has_ic_fills_f_dc ? */
39#define cpu_has_nofpuex 0
40/* #define cpu_has_64bits ? */
41/* #define cpu_has_64bit_zero_reg ? */
42/* #define cpu_has_inclusive_pcaches ? */
43#define cpu_icache_snoops_remote_store 1
44#endif
45
46#ifdef CONFIG_CPU_MIPS64
47#define cpu_has_tlb 1
48#define cpu_has_4kex 1
49#define cpu_has_4k_cache 1
50/* #define cpu_has_fpu ? */
51/* #define cpu_has_32fpr ? */
52#define cpu_has_counter 1
53/* #define cpu_has_watch ? */
54#define cpu_has_divec 1
55#define cpu_has_vce 0
56/* #define cpu_has_cache_cdex_p ? */
57/* #define cpu_has_cache_cdex_s ? */
58/* #define cpu_has_prefetch ? */
59#define cpu_has_mcheck 1
60/* #define cpu_has_ejtag ? */
61#define cpu_has_llsc 1
62/* #define cpu_has_vtag_icache ? */
63/* #define cpu_has_dc_aliases ? */
64/* #define cpu_has_ic_fills_f_dc ? */
65#define cpu_has_nofpuex 0
66/* #define cpu_has_64bits ? */
67/* #define cpu_has_64bit_zero_reg ? */
68/* #define cpu_has_inclusive_pcaches ? */
69#define cpu_icache_snoops_remote_store 1
70#endif
71
72#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-malta/irq.h b/arch/mips/include/asm/mach-malta/irq.h
new file mode 100644
index 000000000000..9b9da26683c2
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/irq.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_MACH_MIPS_IRQ_H
2#define __ASM_MACH_MIPS_IRQ_H
3
4
5#define NR_IRQS 256
6
7#include_next <irq.h>
8
9#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
new file mode 100644
index 000000000000..0b793e7bf67e
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
@@ -0,0 +1,52 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Chris Dearman (chris@mips.com)
7 * Copyright (C) 2007 Mips Technologies, Inc.
8 */
9#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
10#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
11
12 .macro kernel_entry_setup
13#ifdef CONFIG_MIPS_MT_SMTC
14 mfc0 t0, CP0_CONFIG
15 bgez t0, 9f
16 mfc0 t0, CP0_CONFIG, 1
17 bgez t0, 9f
18 mfc0 t0, CP0_CONFIG, 2
19 bgez t0, 9f
20 mfc0 t0, CP0_CONFIG, 3
21 and t0, 1<<2
22 bnez t0, 0f
239:
24 /* Assume we came from YAMON... */
25 PTR_LA v0, 0x9fc00534 /* YAMON print */
26 lw v0, (v0)
27 move a0, zero
28 PTR_LA a1, nonmt_processor
29 jal v0
30
31 PTR_LA v0, 0x9fc00520 /* YAMON exit */
32 lw v0, (v0)
33 li a0, 1
34 jal v0
35
361: b 1b
37
38 __INITDATA
39nonmt_processor:
40 .asciz "SMTC kernel requires the MT ASE to run\n"
41 __FINIT
420:
43#endif
44 .endm
45
46/*
47 * Do SMP slave processor setup necessary before we can safely execute C code.
48 */
49 .macro smp_slave_setup
50 .endm
51
52#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-malta/mach-gt64120.h b/arch/mips/include/asm/mach-malta/mach-gt64120.h
new file mode 100644
index 000000000000..0f863148f3b6
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/mach-gt64120.h
@@ -0,0 +1,19 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H
9#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H
10
11#define MIPS_GT_BASE 0x1be00000
12
13extern unsigned long _pcictrl_gt64120;
14/*
15 * GT64120 config space base address
16 */
17#define GT64120_BASE _pcictrl_gt64120
18
19#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
diff --git a/arch/mips/include/asm/mach-malta/mc146818rtc.h b/arch/mips/include/asm/mach-malta/mc146818rtc.h
new file mode 100644
index 000000000000..ea612f37f614
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/mc146818rtc.h
@@ -0,0 +1,48 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Copyright (C) 2003 by Ralf Baechle
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * RTC routines for Malta style attached PIIX4 device, which contains a
20 * Motorola MC146818A-compatible Real Time Clock.
21 */
22#ifndef __ASM_MACH_MALTA_MC146818RTC_H
23#define __ASM_MACH_MALTA_MC146818RTC_H
24
25#include <asm/io.h>
26#include <asm/mips-boards/generic.h>
27#include <asm/mips-boards/malta.h>
28
29#define RTC_PORT(x) (0x70 + (x))
30#define RTC_IRQ 8
31
32static inline unsigned char CMOS_READ(unsigned long addr)
33{
34 outb(addr, MALTA_RTC_ADR_REG);
35 return inb(MALTA_RTC_DAT_REG);
36}
37
38static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
39{
40 outb(addr, MALTA_RTC_ADR_REG);
41 outb(data, MALTA_RTC_DAT_REG);
42}
43
44#define RTC_ALWAYS_BCD 0
45
46#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
47
48#endif /* __ASM_MACH_MALTA_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
new file mode 100644
index 000000000000..7c6931d5f45f
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
9#define __ASM_MIPS_MACH_MIPS_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 15:04:35 -0500