1 files changed, 0 insertions, 91 deletions
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
deleted file mode 100644
index d3cce7326dd4..000000000000
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * AMD Alchemy DBAu1200 Reference Board
- * Board register defines.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_DB1200_H
-#define __ASM_DB1200_H
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-/* Bit positions for the different interrupt sources */
-#define BCSR_INT_IDE            0x0001
-#define BCSR_INT_ETH            0x0002
-#define BCSR_INT_PC0            0x0004
-#define BCSR_INT_PC0STSCHG      0x0008
-#define BCSR_INT_PC1            0x0010
-#define BCSR_INT_PC1STSCHG      0x0020
-#define BCSR_INT_DC             0x0040
-#define BCSR_INT_FLASHBUSY      0x0080
-#define BCSR_INT_PC0INSERT      0x0100
-#define BCSR_INT_PC0EJECT       0x0200
-#define BCSR_INT_PC1INSERT      0x0400
-#define BCSR_INT_PC1EJECT       0x0800
-#define BCSR_INT_SD0INSERT      0x1000
-#define BCSR_INT_SD0EJECT       0x2000
-#define BCSR_INT_SD1INSERT      0x4000
-#define BCSR_INT_SD1EJECT       0x8000
-#define IDE_REG_SHIFT           5
-#define DB1200_IDE_PHYS_ADDR    0x18800000
-#define DB1200_IDE_PHYS_LEN     (16 << IDE_REG_SHIFT)
-#define DB1200_ETH_PHYS_ADDR    0x19000300
-#define DB1200_NAND_PHYS_ADDR   0x20000000
-#define PB1200_IDE_PHYS_ADDR    0x0C800000
-#define PB1200_ETH_PHYS_ADDR    0x0D000300
-#define PB1200_NAND_PHYS_ADDR   0x1C000000
-/*
- * External Interrupts for DBAu1200 as of 8/6/2004.
- * Bit positions in the CPLD registers can be calculated by taking
- * the interrupt define and subtracting the DB1200_INT_BEGIN value.
- *
- *   Example: IDE bis pos is  = 64 - 64
- *            ETH bit pos is  = 65 - 64
- */
-enum external_db1200_ints {
-        DB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
-        DB1200_IDE_INT          = DB1200_INT_BEGIN,
-        DB1200_ETH_INT,
-        DB1200_PC0_INT,
-        DB1200_PC0_STSCHG_INT,
-        DB1200_PC1_INT,
-        DB1200_PC1_STSCHG_INT,
-        DB1200_DC_INT,
-        DB1200_FLASHBUSY_INT,
-        DB1200_PC0_INSERT_INT,
-        DB1200_PC0_EJECT_INT,
-        DB1200_PC1_INSERT_INT,
-        DB1200_PC1_EJECT_INT,
-        DB1200_SD0_INSERT_INT,
-        DB1200_SD0_EJECT_INT,
-        PB1200_SD1_INSERT_INT,
-        PB1200_SD1_EJECT_INT,
-        DB1200_INT_END          = DB1200_INT_BEGIN + 15,
-};
-#endif /* __ASM_DB1200_H */

diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h deleted file mode 100644 index d3cce7326dd4..000000000000 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ /dev/null
@@ -1,91 +0,0 @@
1	/*
2	* AMD Alchemy DBAu1200 Reference Board
3	* Board register defines.
4	*
5	* ########################################################################
6	*
7	* This program is free software; you can distribute it and/or modify it
8	* under the terms of the GNU General Public License (Version 2) as
9	* published by the Free Software Foundation.
10	*
11	* This program is distributed in the hope it will be useful, but WITHOUT
12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14	* for more details.
15	*
16	* You should have received a copy of the GNU General Public License along
17	* with this program; if not, write to the Free Software Foundation, Inc.,
18	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19	*
20	* ########################################################################
21	*
22	*
23	*/
24	#ifndef __ASM_DB1200_H
25	#define __ASM_DB1200_H
26
27	#include <linux/types.h>
28	#include <asm/mach-au1x00/au1000.h>
29	#include <asm/mach-au1x00/au1xxx_psc.h>
30
31	/* Bit positions for the different interrupt sources */
32	#define BCSR_INT_IDE 0x0001
33	#define BCSR_INT_ETH 0x0002
34	#define BCSR_INT_PC0 0x0004
35	#define BCSR_INT_PC0STSCHG 0x0008
36	#define BCSR_INT_PC1 0x0010
37	#define BCSR_INT_PC1STSCHG 0x0020
38	#define BCSR_INT_DC 0x0040
39	#define BCSR_INT_FLASHBUSY 0x0080
40	#define BCSR_INT_PC0INSERT 0x0100
41	#define BCSR_INT_PC0EJECT 0x0200
42	#define BCSR_INT_PC1INSERT 0x0400
43	#define BCSR_INT_PC1EJECT 0x0800
44	#define BCSR_INT_SD0INSERT 0x1000
45	#define BCSR_INT_SD0EJECT 0x2000
46	#define BCSR_INT_SD1INSERT 0x4000
47	#define BCSR_INT_SD1EJECT 0x8000
48
49	#define IDE_REG_SHIFT 5
50
51	#define DB1200_IDE_PHYS_ADDR 0x18800000
52	#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
53	#define DB1200_ETH_PHYS_ADDR 0x19000300
54	#define DB1200_NAND_PHYS_ADDR 0x20000000
55
56	#define PB1200_IDE_PHYS_ADDR 0x0C800000
57	#define PB1200_ETH_PHYS_ADDR 0x0D000300
58	#define PB1200_NAND_PHYS_ADDR 0x1C000000
59
60	/*
61	* External Interrupts for DBAu1200 as of 8/6/2004.
62	* Bit positions in the CPLD registers can be calculated by taking
63	* the interrupt define and subtracting the DB1200_INT_BEGIN value.
64	*
65	* Example: IDE bis pos is = 64 - 64
66	* ETH bit pos is = 65 - 64
67	*/
68	enum external_db1200_ints {
69	DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
70
71	DB1200_IDE_INT = DB1200_INT_BEGIN,
72	DB1200_ETH_INT,
73	DB1200_PC0_INT,
74	DB1200_PC0_STSCHG_INT,
75	DB1200_PC1_INT,
76	DB1200_PC1_STSCHG_INT,
77	DB1200_DC_INT,
78	DB1200_FLASHBUSY_INT,
79	DB1200_PC0_INSERT_INT,
80	DB1200_PC0_EJECT_INT,
81	DB1200_PC1_INSERT_INT,
82	DB1200_PC1_EJECT_INT,
83	DB1200_SD0_INSERT_INT,
84	DB1200_SD0_EJECT_INT,
85	PB1200_SD1_INSERT_INT,
86	PB1200_SD1_EJECT_INT,
87
88	DB1200_INT_END = DB1200_INT_BEGIN + 15,
89	};
90
91	#endif /* __ASM_DB1200_H */