4 files changed, 214 insertions, 10 deletions

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 22390a2a0661..19f9134bfe2f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -187,7 +187,10 @@ enum bcm63xx_regs_set {
 #define BCM_6358_RSET_SPI_SIZE          1804
 #define BCM_6368_RSET_SPI_SIZE          1804
 #define RSET_ENET_SIZE                  2048
-#define RSET_ENETDMA_SIZE               2048
+#define RSET_ENETDMA_SIZE               256
+#define RSET_6345_ENETDMA_SIZE          64
+#define RSET_ENETDMAC_SIZE(chans)       (16 * (chans))
+#define RSET_ENETDMAS_SIZE(chans)       (16 * (chans))
 #define RSET_ENETSW_SIZE                65536
 #define RSET_UART_SIZE                  24
 #define RSET_UDC_SIZE                   256
@@ -361,7 +364,7 @@ enum bcm63xx_regs_set {
 #define BCM_6345_USBDMA_BASE            (0xfffe2800)
 #define BCM_6345_ENET0_BASE             (0xfffe1800)
 #define BCM_6345_ENETDMA_BASE           (0xfffe2800)
-#define BCM_6345_ENETDMAC_BASE          (0xfffe2900)
+#define BCM_6345_ENETDMAC_BASE          (0xfffe2840)
 #define BCM_6345_ENETDMAS_BASE          (0xfffe2a00)
 #define BCM_6345_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE            (0xfffe2028)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
index d53f611184b9..753953e86242 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -4,6 +4,8 @@
 #include <linux/if_ether.h>
 #include <linux/init.h>
 
+#include <bcm63xx_regs.h>
+
 /*
  * on board ethernet platform data
  */
@@ -37,9 +39,129 @@ struct bcm63xx_enet_platform_data {
                                           int phy_id, int reg),
                           void (*mii_write)(struct net_device *dev,
                                             int phy_id, int reg, int val));
+
+        /* DMA channel enable mask */
+        u32 dma_chan_en_mask;
+
+        /* DMA channel interrupt mask */
+        u32 dma_chan_int_mask;
+
+        /* DMA engine has internal SRAM */
+        bool dma_has_sram;
+
+        /* DMA channel register width */
+        unsigned int dma_chan_width;
+
+        /* DMA descriptor shift */
+        unsigned int dma_desc_shift;
+};
+
+/*
+ * on board ethernet switch platform data
+ */
+#define ENETSW_MAX_PORT 8
+#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
+#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
+
+#define ENETSW_RGMII_PORT0      4
+
+struct bcm63xx_enetsw_port {
+        int             used;
+        int             phy_id;
+
+        int             bypass_link;
+        int             force_speed;
+        int             force_duplex_full;
+
+        const char      *name;
+};
+
+struct bcm63xx_enetsw_platform_data {
+        char mac_addr[ETH_ALEN];
+        int num_ports;
+        struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
+
+        /* DMA channel enable mask */
+        u32 dma_chan_en_mask;
+
+        /* DMA channel interrupt mask */
+        u32 dma_chan_int_mask;
+
+        /* DMA channel register width */
+        unsigned int dma_chan_width;
+
+        /* DMA engine has internal SRAM */
+        bool dma_has_sram;
 };
 
 int __init bcm63xx_enet_register(int unit,
                                  const struct bcm63xx_enet_platform_data *pd);
 
+int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
+
+enum bcm63xx_regs_enetdmac {
+        ENETDMAC_CHANCFG,
+        ENETDMAC_IR,
+        ENETDMAC_IRMASK,
+        ENETDMAC_MAXBURST,
+        ENETDMAC_BUFALLOC,
+        ENETDMAC_RSTART,
+        ENETDMAC_FC,
+        ENETDMAC_LEN,
+};
+
+static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
+{
+#ifdef BCMCPU_RUNTIME_DETECT
+        extern const unsigned long *bcm63xx_regs_enetdmac;
+
+        return bcm63xx_regs_enetdmac[reg];
+#else
+#ifdef CONFIG_BCM63XX_CPU_6345
+        switch (reg) {
+        case ENETDMAC_CHANCFG:
+                return ENETDMA_6345_CHANCFG_REG;
+        case ENETDMAC_IR:
+                return ENETDMA_6345_IR_REG;
+        case ENETDMAC_IRMASK:
+                return ENETDMA_6345_IRMASK_REG;
+        case ENETDMAC_MAXBURST:
+                return ENETDMA_6345_MAXBURST_REG;
+        case ENETDMAC_BUFALLOC:
+                return ENETDMA_6345_BUFALLOC_REG;
+        case ENETDMAC_RSTART:
+                return ENETDMA_6345_RSTART_REG;
+        case ENETDMAC_FC:
+                return ENETDMA_6345_FC_REG;
+        case ENETDMAC_LEN:
+                return ENETDMA_6345_LEN_REG;
+        }
+#endif
+#if defined(CONFIG_BCM63XX_CPU_6328) || \
+        defined(CONFIG_BCM63XX_CPU_6338) || \
+        defined(CONFIG_BCM63XX_CPU_6348) || \
+        defined(CONFIG_BCM63XX_CPU_6358) || \
+        defined(CONFIG_BCM63XX_CPU_6362) || \
+        defined(CONFIG_BCM63XX_CPU_6368)
+        switch (reg) {
+        case ENETDMAC_CHANCFG:
+                return ENETDMAC_CHANCFG_REG;
+        case ENETDMAC_IR:
+                return ENETDMAC_IR_REG;
+        case ENETDMAC_IRMASK:
+                return ENETDMAC_IRMASK_REG;
+        case ENETDMAC_MAXBURST:
+                return ENETDMAC_MAXBURST_REG;
+        case ENETDMAC_BUFALLOC:
+        case ENETDMAC_RSTART:
+        case ENETDMAC_FC:
+        case ENETDMAC_LEN:
+                return 0;
+        }
+#endif
+#endif
+        return 0;
+}
+
+
 #endif /* ! BCM63XX_DEV_ENET_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 018628fe6f15..9875db31d883 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -770,6 +770,8 @@
 /*************************************************************************
  * _REG relative to RSET_ENETDMA
  *************************************************************************/
+#define ENETDMA_CHAN_WIDTH              0x10
+#define ENETDMA_6345_CHAN_WIDTH         0x40
 
 /* Controller Configuration Register */
 #define ENETDMA_CFG_REG                 (0x0)
@@ -825,31 +827,56 @@
 /* State Ram Word 4 */
 #define ENETDMA_SRAM4_REG(x)            (0x20c + (x) * 0x10)
 
+/* Broadcom 6345 ENET DMA definitions */
+#define ENETDMA_6345_CHANCFG_REG        (0x00)
+
+#define ENETDMA_6345_MAXBURST_REG       (0x40)
+
+#define ENETDMA_6345_RSTART_REG         (0x08)
+
+#define ENETDMA_6345_LEN_REG            (0x0C)
+
+#define ENETDMA_6345_IR_REG             (0x14)
+
+#define ENETDMA_6345_IRMASK_REG         (0x18)
+
+#define ENETDMA_6345_FC_REG             (0x1C)
+
+#define ENETDMA_6345_BUFALLOC_REG       (0x20)
+
+/* Shift down for EOP, SOP and WRAP bits */
+#define ENETDMA_6345_DESC_SHIFT         (3)
 
 /*************************************************************************
  * _REG relative to RSET_ENETDMAC
  *************************************************************************/
 
 /* Channel Configuration register */
-#define ENETDMAC_CHANCFG_REG(x)         ((x) * 0x10)
+#define ENETDMAC_CHANCFG_REG            (0x0)
 #define ENETDMAC_CHANCFG_EN_SHIFT       0
 #define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
 #define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT  2
 #define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
+#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
+#define ENETDMAC_CHANCFG_CHAINING_MASK  (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
+#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT  3
+#define ENETDMAC_CHANCFG_WRAP_EN_MASK   (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
+#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
+#define ENETDMAC_CHANCFG_FLOWC_EN_MASK  (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
 
 /* Interrupt Control/Status register */
-#define ENETDMAC_IR_REG(x)              (0x4 + (x) * 0x10)
+#define ENETDMAC_IR_REG                 (0x4)
 #define ENETDMAC_IR_BUFDONE_MASK        (1 << 0)
 #define ENETDMAC_IR_PKTDONE_MASK        (1 << 1)
 #define ENETDMAC_IR_NOTOWNER_MASK       (1 << 2)
 
 /* Interrupt Mask register */
-#define ENETDMAC_IRMASK_REG(x)          (0x8 + (x) * 0x10)
+#define ENETDMAC_IRMASK_REG             (0x8)
 
 /* Maximum Burst Length */
-#define ENETDMAC_MAXBURST_REG(x)        (0xc + (x) * 0x10)
+#define ENETDMAC_MAXBURST_REG           (0xc)
 
 
 /*************************************************************************
@@ -857,26 +884,76 @@
  *************************************************************************/
 
 /* Ring Start Address register */
-#define ENETDMAS_RSTART_REG(x)          ((x) * 0x10)
+#define ENETDMAS_RSTART_REG             (0x0)
 
 /* State Ram Word 2 */
-#define ENETDMAS_SRAM2_REG(x)           (0x4 + (x) * 0x10)
+#define ENETDMAS_SRAM2_REG              (0x4)
 
 /* State Ram Word 3 */
-#define ENETDMAS_SRAM3_REG(x)           (0x8 + (x) * 0x10)
+#define ENETDMAS_SRAM3_REG              (0x8)
 
 /* State Ram Word 4 */
-#define ENETDMAS_SRAM4_REG(x)           (0xc + (x) * 0x10)
+#define ENETDMAS_SRAM4_REG              (0xc)
 
 
 /*************************************************************************
  * _REG relative to RSET_ENETSW
  *************************************************************************/
 
+/* Port traffic control */
+#define ENETSW_PTCTRL_REG(x)            (0x0 + (x))
+#define ENETSW_PTCTRL_RXDIS_MASK        (1 << 0)
+#define ENETSW_PTCTRL_TXDIS_MASK        (1 << 1)
+
+/* Switch mode register */
+#define ENETSW_SWMODE_REG               (0xb)
+#define ENETSW_SWMODE_FWD_EN_MASK       (1 << 1)
+
+/* IMP override Register */
+#define ENETSW_IMPOV_REG                (0xe)
+#define ENETSW_IMPOV_FORCE_MASK         (1 << 7)
+#define ENETSW_IMPOV_TXFLOW_MASK        (1 << 5)
+#define ENETSW_IMPOV_RXFLOW_MASK        (1 << 4)
+#define ENETSW_IMPOV_1000_MASK          (1 << 3)
+#define ENETSW_IMPOV_100_MASK           (1 << 2)
+#define ENETSW_IMPOV_FDX_MASK           (1 << 1)
+#define ENETSW_IMPOV_LINKUP_MASK        (1 << 0)
+
+/* Port override Register */
+#define ENETSW_PORTOV_REG(x)            (0x58 + (x))
+#define ENETSW_PORTOV_ENABLE_MASK       (1 << 6)
+#define ENETSW_PORTOV_TXFLOW_MASK       (1 << 5)
+#define ENETSW_PORTOV_RXFLOW_MASK       (1 << 4)
+#define ENETSW_PORTOV_1000_MASK         (1 << 3)
+#define ENETSW_PORTOV_100_MASK          (1 << 2)
+#define ENETSW_PORTOV_FDX_MASK          (1 << 1)
+#define ENETSW_PORTOV_LINKUP_MASK       (1 << 0)
+
+/* MDIO control register */
+#define ENETSW_MDIOC_REG                (0xb0)
+#define ENETSW_MDIOC_EXT_MASK           (1 << 16)
+#define ENETSW_MDIOC_REG_SHIFT          20
+#define ENETSW_MDIOC_PHYID_SHIFT        25
+#define ENETSW_MDIOC_RD_MASK            (1 << 30)
+#define ENETSW_MDIOC_WR_MASK            (1 << 31)
+
+/* MDIO data register */
+#define ENETSW_MDIOD_REG                (0xb4)
+
+/* Global Management Configuration Register */
+#define ENETSW_GMCR_REG                 (0x200)
+#define ENETSW_GMCR_RST_MIB_MASK        (1 << 0)
+
 /* MIB register */
 #define ENETSW_MIB_REG(x)               (0x2800 + (x) * 4)
 #define ENETSW_MIB_REG_COUNT            47
 
+/* Jumbo control register port mask register */
+#define ENETSW_JMBCTL_PORT_REG          (0x4004)
+
+/* Jumbo control mib good frame register */
+#define ENETSW_JMBCTL_MAXSIZE_REG       (0x4008)
+
 
 /*************************************************************************
  * _REG relative to RSET_OHCI_PRIV
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index 5981fe0c3dfb..b86a0efba665 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -24,6 +24,7 @@ struct board_info {
         /* enabled feature/device */
         unsigned int    has_enet0:1;
         unsigned int    has_enet1:1;
+        unsigned int    has_enetsw:1;
         unsigned int    has_pci:1;
         unsigned int    has_pccard:1;
         unsigned int    has_ohci0:1;
@@ -36,6 +37,7 @@ struct board_info {
         /* ethernet config */
         struct bcm63xx_enet_platform_data enet0;
         struct bcm63xx_enet_platform_data enet1;
+        struct bcm63xx_enetsw_platform_data enetsw;
 
         /* USB config */
         struct bcm63xx_usbd_platform_data usbd;