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Diffstat (limited to 'arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h')
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h597
1 files changed, 382 insertions, 215 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 96a2391ad85b..5b8d15bb5fe8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
13#define BCM6345_CPU_ID 0x6345 13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348 14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358 15#define BCM6358_CPU_ID 0x6358
16#define BCM6368_CPU_ID 0x6368
16 17
17void __init bcm63xx_cpu_init(void); 18void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void); 19u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
71# define BCMCPU_IS_6358() (0) 72# define BCMCPU_IS_6358() (0)
72#endif 73#endif
73 74
75#ifdef CONFIG_BCM63XX_CPU_6368
76# ifdef bcm63xx_get_cpu_id
77# undef bcm63xx_get_cpu_id
78# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
79# define BCMCPU_RUNTIME_DETECT
80# else
81# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
82# endif
83# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
84#else
85# define BCMCPU_IS_6368() (0)
86#endif
87
74#ifndef bcm63xx_get_cpu_id 88#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured" 89#error "No CPU support configured"
76#endif 90#endif
@@ -88,6 +102,7 @@ enum bcm63xx_regs_set {
88 RSET_UART1, 102 RSET_UART1,
89 RSET_GPIO, 103 RSET_GPIO,
90 RSET_SPI, 104 RSET_SPI,
105 RSET_SPI2,
91 RSET_UDC0, 106 RSET_UDC0,
92 RSET_OHCI0, 107 RSET_OHCI0,
93 RSET_OHCI_PRIV, 108 RSET_OHCI_PRIV,
@@ -98,10 +113,23 @@ enum bcm63xx_regs_set {
98 RSET_ENET0, 113 RSET_ENET0,
99 RSET_ENET1, 114 RSET_ENET1,
100 RSET_ENETDMA, 115 RSET_ENETDMA,
116 RSET_ENETDMAC,
117 RSET_ENETDMAS,
118 RSET_ENETSW,
101 RSET_EHCI0, 119 RSET_EHCI0,
102 RSET_SDRAM, 120 RSET_SDRAM,
103 RSET_MEMC, 121 RSET_MEMC,
104 RSET_DDR, 122 RSET_DDR,
123 RSET_M2M,
124 RSET_ATM,
125 RSET_XTM,
126 RSET_XTMDMA,
127 RSET_XTMDMAC,
128 RSET_XTMDMAS,
129 RSET_PCM,
130 RSET_PCMDMA,
131 RSET_PCMDMAC,
132 RSET_PCMDMAS,
105}; 133};
106 134
107#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 135#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
@@ -109,11 +137,18 @@ enum bcm63xx_regs_set {
109#define RSET_WDT_SIZE 12 137#define RSET_WDT_SIZE 12
110#define RSET_ENET_SIZE 2048 138#define RSET_ENET_SIZE 2048
111#define RSET_ENETDMA_SIZE 2048 139#define RSET_ENETDMA_SIZE 2048
140#define RSET_ENETSW_SIZE 65536
112#define RSET_UART_SIZE 24 141#define RSET_UART_SIZE 24
113#define RSET_UDC_SIZE 256 142#define RSET_UDC_SIZE 256
114#define RSET_OHCI_SIZE 256 143#define RSET_OHCI_SIZE 256
115#define RSET_EHCI_SIZE 256 144#define RSET_EHCI_SIZE 256
116#define RSET_PCMCIA_SIZE 12 145#define RSET_PCMCIA_SIZE 12
146#define RSET_M2M_SIZE 256
147#define RSET_ATM_SIZE 4096
148#define RSET_XTM_SIZE 10240
149#define RSET_XTMDMA_SIZE 256
150#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
151#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
117 152
118/* 153/*
119 * 6338 register sets base address 154 * 6338 register sets base address
@@ -127,6 +162,7 @@ enum bcm63xx_regs_set {
127#define BCM_6338_UART1_BASE (0xdeadbeef) 162#define BCM_6338_UART1_BASE (0xdeadbeef)
128#define BCM_6338_GPIO_BASE (0xfffe0400) 163#define BCM_6338_GPIO_BASE (0xfffe0400)
129#define BCM_6338_SPI_BASE (0xfffe0c00) 164#define BCM_6338_SPI_BASE (0xfffe0c00)
165#define BCM_6338_SPI2_BASE (0xdeadbeef)
130#define BCM_6338_UDC0_BASE (0xdeadbeef) 166#define BCM_6338_UDC0_BASE (0xdeadbeef)
131#define BCM_6338_USBDMA_BASE (0xfffe2400) 167#define BCM_6338_USBDMA_BASE (0xfffe2400)
132#define BCM_6338_OHCI0_BASE (0xdeadbeef) 168#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@@ -136,15 +172,27 @@ enum bcm63xx_regs_set {
136#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 172#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
137#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 173#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
138#define BCM_6338_DSL_BASE (0xfffe1000) 174#define BCM_6338_DSL_BASE (0xfffe1000)
139#define BCM_6338_SAR_BASE (0xfffe2000)
140#define BCM_6338_UBUS_BASE (0xdeadbeef) 175#define BCM_6338_UBUS_BASE (0xdeadbeef)
141#define BCM_6338_ENET0_BASE (0xfffe2800) 176#define BCM_6338_ENET0_BASE (0xfffe2800)
142#define BCM_6338_ENET1_BASE (0xdeadbeef) 177#define BCM_6338_ENET1_BASE (0xdeadbeef)
143#define BCM_6338_ENETDMA_BASE (0xfffe2400) 178#define BCM_6338_ENETDMA_BASE (0xfffe2400)
179#define BCM_6338_ENETDMAC_BASE (0xfffe2500)
180#define BCM_6338_ENETDMAS_BASE (0xfffe2600)
181#define BCM_6338_ENETSW_BASE (0xdeadbeef)
144#define BCM_6338_EHCI0_BASE (0xdeadbeef) 182#define BCM_6338_EHCI0_BASE (0xdeadbeef)
145#define BCM_6338_SDRAM_BASE (0xfffe3100) 183#define BCM_6338_SDRAM_BASE (0xfffe3100)
146#define BCM_6338_MEMC_BASE (0xdeadbeef) 184#define BCM_6338_MEMC_BASE (0xdeadbeef)
147#define BCM_6338_DDR_BASE (0xdeadbeef) 185#define BCM_6338_DDR_BASE (0xdeadbeef)
186#define BCM_6338_M2M_BASE (0xdeadbeef)
187#define BCM_6338_ATM_BASE (0xfffe2000)
188#define BCM_6338_XTM_BASE (0xdeadbeef)
189#define BCM_6338_XTMDMA_BASE (0xdeadbeef)
190#define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
191#define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
192#define BCM_6338_PCM_BASE (0xdeadbeef)
193#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
194#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
195#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
148 196
149/* 197/*
150 * 6345 register sets base address 198 * 6345 register sets base address
@@ -158,24 +206,37 @@ enum bcm63xx_regs_set {
158#define BCM_6345_UART1_BASE (0xdeadbeef) 206#define BCM_6345_UART1_BASE (0xdeadbeef)
159#define BCM_6345_GPIO_BASE (0xfffe0400) 207#define BCM_6345_GPIO_BASE (0xfffe0400)
160#define BCM_6345_SPI_BASE (0xdeadbeef) 208#define BCM_6345_SPI_BASE (0xdeadbeef)
209#define BCM_6345_SPI2_BASE (0xdeadbeef)
161#define BCM_6345_UDC0_BASE (0xdeadbeef) 210#define BCM_6345_UDC0_BASE (0xdeadbeef)
162#define BCM_6345_USBDMA_BASE (0xfffe2800) 211#define BCM_6345_USBDMA_BASE (0xfffe2800)
163#define BCM_6345_ENET0_BASE (0xfffe1800) 212#define BCM_6345_ENET0_BASE (0xfffe1800)
164#define BCM_6345_ENETDMA_BASE (0xfffe2800) 213#define BCM_6345_ENETDMA_BASE (0xfffe2800)
214#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
215#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
216#define BCM_6345_ENETSW_BASE (0xdeadbeef)
165#define BCM_6345_PCMCIA_BASE (0xfffe2028) 217#define BCM_6345_PCMCIA_BASE (0xfffe2028)
166#define BCM_6345_MPI_BASE (0xdeadbeef) 218#define BCM_6345_MPI_BASE (0xfffe2000)
167#define BCM_6345_OHCI0_BASE (0xfffe2100) 219#define BCM_6345_OHCI0_BASE (0xfffe2100)
168#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 220#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
169#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 221#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
170#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 222#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
171#define BCM_6345_DSL_BASE (0xdeadbeef) 223#define BCM_6345_DSL_BASE (0xdeadbeef)
172#define BCM_6345_SAR_BASE (0xdeadbeef)
173#define BCM_6345_UBUS_BASE (0xdeadbeef) 224#define BCM_6345_UBUS_BASE (0xdeadbeef)
174#define BCM_6345_ENET1_BASE (0xdeadbeef) 225#define BCM_6345_ENET1_BASE (0xdeadbeef)
175#define BCM_6345_EHCI0_BASE (0xdeadbeef) 226#define BCM_6345_EHCI0_BASE (0xdeadbeef)
176#define BCM_6345_SDRAM_BASE (0xfffe2300) 227#define BCM_6345_SDRAM_BASE (0xfffe2300)
177#define BCM_6345_MEMC_BASE (0xdeadbeef) 228#define BCM_6345_MEMC_BASE (0xdeadbeef)
178#define BCM_6345_DDR_BASE (0xdeadbeef) 229#define BCM_6345_DDR_BASE (0xdeadbeef)
230#define BCM_6345_M2M_BASE (0xdeadbeef)
231#define BCM_6345_ATM_BASE (0xfffe4000)
232#define BCM_6345_XTM_BASE (0xdeadbeef)
233#define BCM_6345_XTMDMA_BASE (0xdeadbeef)
234#define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
235#define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
236#define BCM_6345_PCM_BASE (0xdeadbeef)
237#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
238#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
239#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
179 240
180/* 241/*
181 * 6348 register sets base address 242 * 6348 register sets base address
@@ -188,6 +249,7 @@ enum bcm63xx_regs_set {
188#define BCM_6348_UART1_BASE (0xdeadbeef) 249#define BCM_6348_UART1_BASE (0xdeadbeef)
189#define BCM_6348_GPIO_BASE (0xfffe0400) 250#define BCM_6348_GPIO_BASE (0xfffe0400)
190#define BCM_6348_SPI_BASE (0xfffe0c00) 251#define BCM_6348_SPI_BASE (0xfffe0c00)
252#define BCM_6348_SPI2_BASE (0xdeadbeef)
191#define BCM_6348_UDC0_BASE (0xfffe1000) 253#define BCM_6348_UDC0_BASE (0xfffe1000)
192#define BCM_6348_OHCI0_BASE (0xfffe1b00) 254#define BCM_6348_OHCI0_BASE (0xfffe1b00)
193#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 255#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
@@ -195,14 +257,27 @@ enum bcm63xx_regs_set {
195#define BCM_6348_MPI_BASE (0xfffe2000) 257#define BCM_6348_MPI_BASE (0xfffe2000)
196#define BCM_6348_PCMCIA_BASE (0xfffe2054) 258#define BCM_6348_PCMCIA_BASE (0xfffe2054)
197#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 259#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
260#define BCM_6348_M2M_BASE (0xfffe2800)
198#define BCM_6348_DSL_BASE (0xfffe3000) 261#define BCM_6348_DSL_BASE (0xfffe3000)
199#define BCM_6348_ENET0_BASE (0xfffe6000) 262#define BCM_6348_ENET0_BASE (0xfffe6000)
200#define BCM_6348_ENET1_BASE (0xfffe6800) 263#define BCM_6348_ENET1_BASE (0xfffe6800)
201#define BCM_6348_ENETDMA_BASE (0xfffe7000) 264#define BCM_6348_ENETDMA_BASE (0xfffe7000)
265#define BCM_6348_ENETDMAC_BASE (0xfffe7100)
266#define BCM_6348_ENETDMAS_BASE (0xfffe7200)
267#define BCM_6348_ENETSW_BASE (0xdeadbeef)
202#define BCM_6348_EHCI0_BASE (0xdeadbeef) 268#define BCM_6348_EHCI0_BASE (0xdeadbeef)
203#define BCM_6348_SDRAM_BASE (0xfffe2300) 269#define BCM_6348_SDRAM_BASE (0xfffe2300)
204#define BCM_6348_MEMC_BASE (0xdeadbeef) 270#define BCM_6348_MEMC_BASE (0xdeadbeef)
205#define BCM_6348_DDR_BASE (0xdeadbeef) 271#define BCM_6348_DDR_BASE (0xdeadbeef)
272#define BCM_6348_ATM_BASE (0xfffe4000)
273#define BCM_6348_XTM_BASE (0xdeadbeef)
274#define BCM_6348_XTMDMA_BASE (0xdeadbeef)
275#define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
276#define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
277#define BCM_6348_PCM_BASE (0xdeadbeef)
278#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
279#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
280#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
206 281
207/* 282/*
208 * 6358 register sets base address 283 * 6358 register sets base address
@@ -215,6 +290,7 @@ enum bcm63xx_regs_set {
215#define BCM_6358_UART1_BASE (0xfffe0120) 290#define BCM_6358_UART1_BASE (0xfffe0120)
216#define BCM_6358_GPIO_BASE (0xfffe0080) 291#define BCM_6358_GPIO_BASE (0xfffe0080)
217#define BCM_6358_SPI_BASE (0xdeadbeef) 292#define BCM_6358_SPI_BASE (0xdeadbeef)
293#define BCM_6358_SPI2_BASE (0xfffe0800)
218#define BCM_6358_UDC0_BASE (0xfffe0800) 294#define BCM_6358_UDC0_BASE (0xfffe0800)
219#define BCM_6358_OHCI0_BASE (0xfffe1400) 295#define BCM_6358_OHCI0_BASE (0xfffe1400)
220#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 296#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
@@ -222,214 +298,175 @@ enum bcm63xx_regs_set {
222#define BCM_6358_MPI_BASE (0xfffe1000) 298#define BCM_6358_MPI_BASE (0xfffe1000)
223#define BCM_6358_PCMCIA_BASE (0xfffe1054) 299#define BCM_6358_PCMCIA_BASE (0xfffe1054)
224#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 300#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
301#define BCM_6358_M2M_BASE (0xdeadbeef)
225#define BCM_6358_DSL_BASE (0xfffe3000) 302#define BCM_6358_DSL_BASE (0xfffe3000)
226#define BCM_6358_ENET0_BASE (0xfffe4000) 303#define BCM_6358_ENET0_BASE (0xfffe4000)
227#define BCM_6358_ENET1_BASE (0xfffe4800) 304#define BCM_6358_ENET1_BASE (0xfffe4800)
228#define BCM_6358_ENETDMA_BASE (0xfffe5000) 305#define BCM_6358_ENETDMA_BASE (0xfffe5000)
306#define BCM_6358_ENETDMAC_BASE (0xfffe5100)
307#define BCM_6358_ENETDMAS_BASE (0xfffe5200)
308#define BCM_6358_ENETSW_BASE (0xdeadbeef)
229#define BCM_6358_EHCI0_BASE (0xfffe1300) 309#define BCM_6358_EHCI0_BASE (0xfffe1300)
230#define BCM_6358_SDRAM_BASE (0xdeadbeef) 310#define BCM_6358_SDRAM_BASE (0xdeadbeef)
231#define BCM_6358_MEMC_BASE (0xfffe1200) 311#define BCM_6358_MEMC_BASE (0xfffe1200)
232#define BCM_6358_DDR_BASE (0xfffe12a0) 312#define BCM_6358_DDR_BASE (0xfffe12a0)
313#define BCM_6358_ATM_BASE (0xfffe2000)
314#define BCM_6358_XTM_BASE (0xdeadbeef)
315#define BCM_6358_XTMDMA_BASE (0xdeadbeef)
316#define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
317#define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
318#define BCM_6358_PCM_BASE (0xfffe1600)
319#define BCM_6358_PCMDMA_BASE (0xfffe1800)
320#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
321#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
322
323
324/*
325 * 6368 register sets base address
326 */
327#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
328#define BCM_6368_PERF_BASE (0xb0000000)
329#define BCM_6368_TIMER_BASE (0xb0000040)
330#define BCM_6368_WDT_BASE (0xb000005c)
331#define BCM_6368_UART0_BASE (0xb0000100)
332#define BCM_6368_UART1_BASE (0xb0000120)
333#define BCM_6368_GPIO_BASE (0xb0000080)
334#define BCM_6368_SPI_BASE (0xdeadbeef)
335#define BCM_6368_SPI2_BASE (0xb0000800)
336#define BCM_6368_UDC0_BASE (0xdeadbeef)
337#define BCM_6368_OHCI0_BASE (0xb0001600)
338#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
339#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
340#define BCM_6368_MPI_BASE (0xb0001000)
341#define BCM_6368_PCMCIA_BASE (0xb0001054)
342#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
343#define BCM_6368_M2M_BASE (0xdeadbeef)
344#define BCM_6368_DSL_BASE (0xdeadbeef)
345#define BCM_6368_ENET0_BASE (0xdeadbeef)
346#define BCM_6368_ENET1_BASE (0xdeadbeef)
347#define BCM_6368_ENETDMA_BASE (0xb0006800)
348#define BCM_6368_ENETDMAC_BASE (0xb0006a00)
349#define BCM_6368_ENETDMAS_BASE (0xb0006c00)
350#define BCM_6368_ENETSW_BASE (0xb0f00000)
351#define BCM_6368_EHCI0_BASE (0xb0001500)
352#define BCM_6368_SDRAM_BASE (0xdeadbeef)
353#define BCM_6368_MEMC_BASE (0xb0001200)
354#define BCM_6368_DDR_BASE (0xb0001280)
355#define BCM_6368_ATM_BASE (0xdeadbeef)
356#define BCM_6368_XTM_BASE (0xb0001800)
357#define BCM_6368_XTMDMA_BASE (0xb0005000)
358#define BCM_6368_XTMDMAC_BASE (0xb0005200)
359#define BCM_6368_XTMDMAS_BASE (0xb0005400)
360#define BCM_6368_PCM_BASE (0xb0004000)
361#define BCM_6368_PCMDMA_BASE (0xb0005800)
362#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
363#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
233 364
234 365
235extern const unsigned long *bcm63xx_regs_base; 366extern const unsigned long *bcm63xx_regs_base;
236 367
368#define __GEN_RSET_BASE(__cpu, __rset) \
369 case RSET_## __rset : \
370 return BCM_## __cpu ##_## __rset ##_BASE;
371
372#define __GEN_RSET(__cpu) \
373 switch (set) { \
374 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
375 __GEN_RSET_BASE(__cpu, PERF) \
376 __GEN_RSET_BASE(__cpu, TIMER) \
377 __GEN_RSET_BASE(__cpu, WDT) \
378 __GEN_RSET_BASE(__cpu, UART0) \
379 __GEN_RSET_BASE(__cpu, UART1) \
380 __GEN_RSET_BASE(__cpu, GPIO) \
381 __GEN_RSET_BASE(__cpu, SPI) \
382 __GEN_RSET_BASE(__cpu, SPI2) \
383 __GEN_RSET_BASE(__cpu, UDC0) \
384 __GEN_RSET_BASE(__cpu, OHCI0) \
385 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
386 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
387 __GEN_RSET_BASE(__cpu, MPI) \
388 __GEN_RSET_BASE(__cpu, PCMCIA) \
389 __GEN_RSET_BASE(__cpu, DSL) \
390 __GEN_RSET_BASE(__cpu, ENET0) \
391 __GEN_RSET_BASE(__cpu, ENET1) \
392 __GEN_RSET_BASE(__cpu, ENETDMA) \
393 __GEN_RSET_BASE(__cpu, ENETDMAC) \
394 __GEN_RSET_BASE(__cpu, ENETDMAS) \
395 __GEN_RSET_BASE(__cpu, ENETSW) \
396 __GEN_RSET_BASE(__cpu, EHCI0) \
397 __GEN_RSET_BASE(__cpu, SDRAM) \
398 __GEN_RSET_BASE(__cpu, MEMC) \
399 __GEN_RSET_BASE(__cpu, DDR) \
400 __GEN_RSET_BASE(__cpu, M2M) \
401 __GEN_RSET_BASE(__cpu, ATM) \
402 __GEN_RSET_BASE(__cpu, XTM) \
403 __GEN_RSET_BASE(__cpu, XTMDMA) \
404 __GEN_RSET_BASE(__cpu, XTMDMAC) \
405 __GEN_RSET_BASE(__cpu, XTMDMAS) \
406 __GEN_RSET_BASE(__cpu, PCM) \
407 __GEN_RSET_BASE(__cpu, PCMDMA) \
408 __GEN_RSET_BASE(__cpu, PCMDMAC) \
409 __GEN_RSET_BASE(__cpu, PCMDMAS) \
410 }
411
412#define __GEN_CPU_REGS_TABLE(__cpu) \
413 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
414 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
415 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
416 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
417 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
418 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
419 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
420 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
421 [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
422 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
423 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
424 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
425 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
426 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
427 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
428 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
429 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
430 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
431 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
432 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
433 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
434 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
435 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
436 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
437 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
438 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
439 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
440 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
441 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
442 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
443 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
444 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
445 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
446 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
447 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
448 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
449
450
237static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 451static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
238{ 452{
239#ifdef BCMCPU_RUNTIME_DETECT 453#ifdef BCMCPU_RUNTIME_DETECT
240 return bcm63xx_regs_base[set]; 454 return bcm63xx_regs_base[set];
241#else 455#else
242#ifdef CONFIG_BCM63XX_CPU_6338 456#ifdef CONFIG_BCM63XX_CPU_6338
243 switch (set) { 457 __GEN_RSET(6338)
244 case RSET_DSL_LMEM:
245 return BCM_6338_DSL_LMEM_BASE;
246 case RSET_PERF:
247 return BCM_6338_PERF_BASE;
248 case RSET_TIMER:
249 return BCM_6338_TIMER_BASE;
250 case RSET_WDT:
251 return BCM_6338_WDT_BASE;
252 case RSET_UART0:
253 return BCM_6338_UART0_BASE;
254 case RSET_UART1:
255 return BCM_6338_UART1_BASE;
256 case RSET_GPIO:
257 return BCM_6338_GPIO_BASE;
258 case RSET_SPI:
259 return BCM_6338_SPI_BASE;
260 case RSET_UDC0:
261 return BCM_6338_UDC0_BASE;
262 case RSET_OHCI0:
263 return BCM_6338_OHCI0_BASE;
264 case RSET_OHCI_PRIV:
265 return BCM_6338_OHCI_PRIV_BASE;
266 case RSET_USBH_PRIV:
267 return BCM_6338_USBH_PRIV_BASE;
268 case RSET_MPI:
269 return BCM_6338_MPI_BASE;
270 case RSET_PCMCIA:
271 return BCM_6338_PCMCIA_BASE;
272 case RSET_DSL:
273 return BCM_6338_DSL_BASE;
274 case RSET_ENET0:
275 return BCM_6338_ENET0_BASE;
276 case RSET_ENET1:
277 return BCM_6338_ENET1_BASE;
278 case RSET_ENETDMA:
279 return BCM_6338_ENETDMA_BASE;
280 case RSET_EHCI0:
281 return BCM_6338_EHCI0_BASE;
282 case RSET_SDRAM:
283 return BCM_6338_SDRAM_BASE;
284 case RSET_MEMC:
285 return BCM_6338_MEMC_BASE;
286 case RSET_DDR:
287 return BCM_6338_DDR_BASE;
288 }
289#endif 458#endif
290#ifdef CONFIG_BCM63XX_CPU_6345 459#ifdef CONFIG_BCM63XX_CPU_6345
291 switch (set) { 460 __GEN_RSET(6345)
292 case RSET_DSL_LMEM:
293 return BCM_6345_DSL_LMEM_BASE;
294 case RSET_PERF:
295 return BCM_6345_PERF_BASE;
296 case RSET_TIMER:
297 return BCM_6345_TIMER_BASE;
298 case RSET_WDT:
299 return BCM_6345_WDT_BASE;
300 case RSET_UART0:
301 return BCM_6345_UART0_BASE;
302 case RSET_UART1:
303 return BCM_6345_UART1_BASE;
304 case RSET_GPIO:
305 return BCM_6345_GPIO_BASE;
306 case RSET_SPI:
307 return BCM_6345_SPI_BASE;
308 case RSET_UDC0:
309 return BCM_6345_UDC0_BASE;
310 case RSET_OHCI0:
311 return BCM_6345_OHCI0_BASE;
312 case RSET_OHCI_PRIV:
313 return BCM_6345_OHCI_PRIV_BASE;
314 case RSET_USBH_PRIV:
315 return BCM_6345_USBH_PRIV_BASE;
316 case RSET_MPI:
317 return BCM_6345_MPI_BASE;
318 case RSET_PCMCIA:
319 return BCM_6345_PCMCIA_BASE;
320 case RSET_DSL:
321 return BCM_6345_DSL_BASE;
322 case RSET_ENET0:
323 return BCM_6345_ENET0_BASE;
324 case RSET_ENET1:
325 return BCM_6345_ENET1_BASE;
326 case RSET_ENETDMA:
327 return BCM_6345_ENETDMA_BASE;
328 case RSET_EHCI0:
329 return BCM_6345_EHCI0_BASE;
330 case RSET_SDRAM:
331 return BCM_6345_SDRAM_BASE;
332 case RSET_MEMC:
333 return BCM_6345_MEMC_BASE;
334 case RSET_DDR:
335 return BCM_6345_DDR_BASE;
336 }
337#endif 461#endif
338#ifdef CONFIG_BCM63XX_CPU_6348 462#ifdef CONFIG_BCM63XX_CPU_6348
339 switch (set) { 463 __GEN_RSET(6348)
340 case RSET_DSL_LMEM:
341 return BCM_6348_DSL_LMEM_BASE;
342 case RSET_PERF:
343 return BCM_6348_PERF_BASE;
344 case RSET_TIMER:
345 return BCM_6348_TIMER_BASE;
346 case RSET_WDT:
347 return BCM_6348_WDT_BASE;
348 case RSET_UART0:
349 return BCM_6348_UART0_BASE;
350 case RSET_UART1:
351 return BCM_6348_UART1_BASE;
352 case RSET_GPIO:
353 return BCM_6348_GPIO_BASE;
354 case RSET_SPI:
355 return BCM_6348_SPI_BASE;
356 case RSET_UDC0:
357 return BCM_6348_UDC0_BASE;
358 case RSET_OHCI0:
359 return BCM_6348_OHCI0_BASE;
360 case RSET_OHCI_PRIV:
361 return BCM_6348_OHCI_PRIV_BASE;
362 case RSET_USBH_PRIV:
363 return BCM_6348_USBH_PRIV_BASE;
364 case RSET_MPI:
365 return BCM_6348_MPI_BASE;
366 case RSET_PCMCIA:
367 return BCM_6348_PCMCIA_BASE;
368 case RSET_DSL:
369 return BCM_6348_DSL_BASE;
370 case RSET_ENET0:
371 return BCM_6348_ENET0_BASE;
372 case RSET_ENET1:
373 return BCM_6348_ENET1_BASE;
374 case RSET_ENETDMA:
375 return BCM_6348_ENETDMA_BASE;
376 case RSET_EHCI0:
377 return BCM_6348_EHCI0_BASE;
378 case RSET_SDRAM:
379 return BCM_6348_SDRAM_BASE;
380 case RSET_MEMC:
381 return BCM_6348_MEMC_BASE;
382 case RSET_DDR:
383 return BCM_6348_DDR_BASE;
384 }
385#endif 464#endif
386#ifdef CONFIG_BCM63XX_CPU_6358 465#ifdef CONFIG_BCM63XX_CPU_6358
387 switch (set) { 466 __GEN_RSET(6358)
388 case RSET_DSL_LMEM: 467#endif
389 return BCM_6358_DSL_LMEM_BASE; 468#ifdef CONFIG_BCM63XX_CPU_6368
390 case RSET_PERF: 469 __GEN_RSET(6368)
391 return BCM_6358_PERF_BASE;
392 case RSET_TIMER:
393 return BCM_6358_TIMER_BASE;
394 case RSET_WDT:
395 return BCM_6358_WDT_BASE;
396 case RSET_UART0:
397 return BCM_6358_UART0_BASE;
398 case RSET_UART1:
399 return BCM_6358_UART1_BASE;
400 case RSET_GPIO:
401 return BCM_6358_GPIO_BASE;
402 case RSET_SPI:
403 return BCM_6358_SPI_BASE;
404 case RSET_UDC0:
405 return BCM_6358_UDC0_BASE;
406 case RSET_OHCI0:
407 return BCM_6358_OHCI0_BASE;
408 case RSET_OHCI_PRIV:
409 return BCM_6358_OHCI_PRIV_BASE;
410 case RSET_USBH_PRIV:
411 return BCM_6358_USBH_PRIV_BASE;
412 case RSET_MPI:
413 return BCM_6358_MPI_BASE;
414 case RSET_PCMCIA:
415 return BCM_6358_PCMCIA_BASE;
416 case RSET_ENET0:
417 return BCM_6358_ENET0_BASE;
418 case RSET_ENET1:
419 return BCM_6358_ENET1_BASE;
420 case RSET_ENETDMA:
421 return BCM_6358_ENETDMA_BASE;
422 case RSET_DSL:
423 return BCM_6358_DSL_BASE;
424 case RSET_EHCI0:
425 return BCM_6358_EHCI0_BASE;
426 case RSET_SDRAM:
427 return BCM_6358_SDRAM_BASE;
428 case RSET_MEMC:
429 return BCM_6358_MEMC_BASE;
430 case RSET_DDR:
431 return BCM_6358_DDR_BASE;
432 }
433#endif 470#endif
434#endif 471#endif
435 /* unreached */ 472 /* unreached */
@@ -449,75 +486,114 @@ enum bcm63xx_irq {
449 IRQ_ENET_PHY, 486 IRQ_ENET_PHY,
450 IRQ_OHCI0, 487 IRQ_OHCI0,
451 IRQ_EHCI0, 488 IRQ_EHCI0,
452 IRQ_PCMCIA0,
453 IRQ_ENET0_RXDMA, 489 IRQ_ENET0_RXDMA,
454 IRQ_ENET0_TXDMA, 490 IRQ_ENET0_TXDMA,
455 IRQ_ENET1_RXDMA, 491 IRQ_ENET1_RXDMA,
456 IRQ_ENET1_TXDMA, 492 IRQ_ENET1_TXDMA,
457 IRQ_PCI, 493 IRQ_PCI,
458 IRQ_PCMCIA, 494 IRQ_PCMCIA,
495 IRQ_ATM,
496 IRQ_ENETSW_RXDMA0,
497 IRQ_ENETSW_RXDMA1,
498 IRQ_ENETSW_RXDMA2,
499 IRQ_ENETSW_RXDMA3,
500 IRQ_ENETSW_TXDMA0,
501 IRQ_ENETSW_TXDMA1,
502 IRQ_ENETSW_TXDMA2,
503 IRQ_ENETSW_TXDMA3,
504 IRQ_XTM,
505 IRQ_XTM_DMA0,
459}; 506};
460 507
461/* 508/*
462 * 6338 irqs 509 * 6338 irqs
463 */ 510 */
464#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 511#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
465#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
466#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 512#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
467#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) 513#define BCM_6338_UART1_IRQ 0
468#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 514#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
469#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
470#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
471#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 515#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
516#define BCM_6338_ENET1_IRQ 0
472#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 517#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
473#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) 518#define BCM_6338_OHCI0_IRQ 0
474#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) 519#define BCM_6338_EHCI0_IRQ 0
475#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
476#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
477#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
478#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 520#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
479#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 521#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
480#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) 522#define BCM_6338_ENET1_RXDMA_IRQ 0
523#define BCM_6338_ENET1_TXDMA_IRQ 0
524#define BCM_6338_PCI_IRQ 0
525#define BCM_6338_PCMCIA_IRQ 0
526#define BCM_6338_ATM_IRQ 0
527#define BCM_6338_ENETSW_RXDMA0_IRQ 0
528#define BCM_6338_ENETSW_RXDMA1_IRQ 0
529#define BCM_6338_ENETSW_RXDMA2_IRQ 0
530#define BCM_6338_ENETSW_RXDMA3_IRQ 0
531#define BCM_6338_ENETSW_TXDMA0_IRQ 0
532#define BCM_6338_ENETSW_TXDMA1_IRQ 0
533#define BCM_6338_ENETSW_TXDMA2_IRQ 0
534#define BCM_6338_ENETSW_TXDMA3_IRQ 0
535#define BCM_6338_XTM_IRQ 0
536#define BCM_6338_XTM_DMA0_IRQ 0
481 537
482/* 538/*
483 * 6345 irqs 539 * 6345 irqs
484 */ 540 */
485#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 541#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
486#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 542#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
543#define BCM_6345_UART1_IRQ 0
487#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 544#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
488#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
489#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
490#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 545#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
546#define BCM_6345_ENET1_IRQ 0
491#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 547#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
548#define BCM_6345_OHCI0_IRQ 0
549#define BCM_6345_EHCI0_IRQ 0
492#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 550#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
493#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 551#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
494#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) 552#define BCM_6345_ENET1_RXDMA_IRQ 0
495#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) 553#define BCM_6345_ENET1_TXDMA_IRQ 0
496#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) 554#define BCM_6345_PCI_IRQ 0
497#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) 555#define BCM_6345_PCMCIA_IRQ 0
498#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) 556#define BCM_6345_ATM_IRQ 0
499#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) 557#define BCM_6345_ENETSW_RXDMA0_IRQ 0
500#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) 558#define BCM_6345_ENETSW_RXDMA1_IRQ 0
501#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) 559#define BCM_6345_ENETSW_RXDMA2_IRQ 0
502#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) 560#define BCM_6345_ENETSW_RXDMA3_IRQ 0
503#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) 561#define BCM_6345_ENETSW_TXDMA0_IRQ 0
562#define BCM_6345_ENETSW_TXDMA1_IRQ 0
563#define BCM_6345_ENETSW_TXDMA2_IRQ 0
564#define BCM_6345_ENETSW_TXDMA3_IRQ 0
565#define BCM_6345_XTM_IRQ 0
566#define BCM_6345_XTM_DMA0_IRQ 0
504 567
505/* 568/*
506 * 6348 irqs 569 * 6348 irqs
507 */ 570 */
508#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 571#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
509#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 572#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
573#define BCM_6348_UART1_IRQ 0
510#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 574#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
511#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
512#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 575#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
576#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
513#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 577#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
514#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 578#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
579#define BCM_6348_EHCI0_IRQ 0
515#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 580#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
516#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 581#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
517#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 582#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
518#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 583#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
519#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
520#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 584#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
585#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
586#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
587#define BCM_6348_ENETSW_RXDMA0_IRQ 0
588#define BCM_6348_ENETSW_RXDMA1_IRQ 0
589#define BCM_6348_ENETSW_RXDMA2_IRQ 0
590#define BCM_6348_ENETSW_RXDMA3_IRQ 0
591#define BCM_6348_ENETSW_TXDMA0_IRQ 0
592#define BCM_6348_ENETSW_TXDMA1_IRQ 0
593#define BCM_6348_ENETSW_TXDMA2_IRQ 0
594#define BCM_6348_ENETSW_TXDMA3_IRQ 0
595#define BCM_6348_XTM_IRQ 0
596#define BCM_6348_XTM_DMA0_IRQ 0
521 597
522/* 598/*
523 * 6358 irqs 599 * 6358 irqs
@@ -525,21 +601,108 @@ enum bcm63xx_irq {
525#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 601#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
526#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 602#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
527#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 603#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
528#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 604#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
529#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
530#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 605#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
606#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
531#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 607#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
608#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
532#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 609#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
533#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 610#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
534#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 611#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
535#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 612#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
536#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 613#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
537#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
538#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 614#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
539#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 615#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
616#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
617#define BCM_6358_ENETSW_RXDMA0_IRQ 0
618#define BCM_6358_ENETSW_RXDMA1_IRQ 0
619#define BCM_6358_ENETSW_RXDMA2_IRQ 0
620#define BCM_6358_ENETSW_RXDMA3_IRQ 0
621#define BCM_6358_ENETSW_TXDMA0_IRQ 0
622#define BCM_6358_ENETSW_TXDMA1_IRQ 0
623#define BCM_6358_ENETSW_TXDMA2_IRQ 0
624#define BCM_6358_ENETSW_TXDMA3_IRQ 0
625#define BCM_6358_XTM_IRQ 0
626#define BCM_6358_XTM_DMA0_IRQ 0
627
628#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
629#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
630#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
631#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
632#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
633#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
634
635/*
636 * 6368 irqs
637 */
638#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
639
640#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
641#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
642#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
643#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
644#define BCM_6368_ENET0_IRQ 0
645#define BCM_6368_ENET1_IRQ 0
646#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
647#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
648#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
649#define BCM_6368_PCMCIA_IRQ 0
650#define BCM_6368_ENET0_RXDMA_IRQ 0
651#define BCM_6368_ENET0_TXDMA_IRQ 0
652#define BCM_6368_ENET1_RXDMA_IRQ 0
653#define BCM_6368_ENET1_TXDMA_IRQ 0
654#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
655#define BCM_6368_ATM_IRQ 0
656#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
657#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
658#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
659#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
660#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
661#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
662#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
663#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
664#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
665#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
666
667#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
668#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
669#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
670#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
671#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
672#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
673#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
674#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
540 675
541extern const int *bcm63xx_irqs; 676extern const int *bcm63xx_irqs;
542 677
678#define __GEN_CPU_IRQ_TABLE(__cpu) \
679 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
680 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
681 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
682 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
683 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
684 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
685 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
686 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
687 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
688 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
689 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
690 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
691 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
692 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
693 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
694 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
695 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
696 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
697 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
698 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
699 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
700 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
701 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
702 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
703 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
704 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
705
543static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 706static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
544{ 707{
545 return bcm63xx_irqs[irq]; 708 return bcm63xx_irqs[irq];
@@ -550,4 +713,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
550 */ 713 */
551unsigned int bcm63xx_get_memory_size(void); 714unsigned int bcm63xx_get_memory_size(void);
552 715
716void bcm63xx_machine_halt(void);
717
718void bcm63xx_machine_reboot(void);
719
553#endif /* !BCM63XX_CPU_H_ */ 720#endif /* !BCM63XX_CPU_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 05:31:49 -0500