1 files changed, 80 insertions, 254 deletions

diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index a6976619160a..f260ebed713b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -161,6 +161,45 @@ static inline int alchemy_get_cputype(void)
         return ALCHEMY_CPU_UNKNOWN;
 }
 
+/* return number of uarts on a given cputype */
+static inline int alchemy_get_uarts(int type)
+{
+        switch (type) {
+        case ALCHEMY_CPU_AU1000:
+                return 4;
+        case ALCHEMY_CPU_AU1500:
+        case ALCHEMY_CPU_AU1200:
+                return 2;
+        case ALCHEMY_CPU_AU1100:
+        case ALCHEMY_CPU_AU1550:
+                return 3;
+        }
+        return 0;
+}
+
+/* enable an UART block if it isn't already */
+static inline void alchemy_uart_enable(u32 uart_phys)
+{
+        void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
+
+        /* reset, enable clock, deassert reset */
+        if ((__raw_readl(addr + 0x100) & 3) != 3) {
+                __raw_writel(0, addr + 0x100);
+                wmb();
+                __raw_writel(1, addr + 0x100);
+                wmb();
+        }
+        __raw_writel(3, addr + 0x100);
+        wmb();
+}
+
+static inline void alchemy_uart_disable(u32 uart_phys)
+{
+        void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
+        __raw_writel(0, addr + 0x100);  /* UART_MOD_CNTRL */
+        wmb();
+}
+
 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
 {
         void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
@@ -180,6 +219,20 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
         wmb();
 }
 
+/* return number of ethernet MACs on a given cputype */
+static inline int alchemy_get_macs(int type)
+{
+        switch (type) {
+        case ALCHEMY_CPU_AU1000:
+        case ALCHEMY_CPU_AU1500:
+        case ALCHEMY_CPU_AU1550:
+                return 2;
+        case ALCHEMY_CPU_AU1100:
+                return 1;
+        }
+        return 0;
+}
+
 /* arch/mips/au1000/common/clocks.c */
 extern void set_au1x00_speed(unsigned int new_freq);
 extern unsigned int get_au1x00_speed(void);
@@ -630,38 +683,42 @@ enum soc_au1200_ints {
 
 /*
  * Physical base addresses for integrated peripherals
+ * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
  */
 
+#define AU1000_AC97_PHYS_ADDR           0x10000000 /* 012 */
+#define AU1000_USBD_PHYS_ADDR           0x10200000 /* 0123 */
+#define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
+#define AU1000_MAC0_PHYS_ADDR           0x10500000 /* 023 */
+#define AU1000_MAC1_PHYS_ADDR           0x10510000 /* 023 */
+#define AU1000_MACEN_PHYS_ADDR          0x10520000 /* 023 */
+#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 24 */
+#define AU1100_SD1_PHYS_ADDR            0x10680000 /* 24 */
+#define AU1000_I2S_PHYS_ADDR            0x11000000 /* 02 */
+#define AU1500_MAC0_PHYS_ADDR           0x11500000 /* 1 */
+#define AU1500_MAC1_PHYS_ADDR           0x11510000 /* 1 */
+#define AU1500_MACEN_PHYS_ADDR          0x11520000 /* 1 */
+#define AU1000_UART0_PHYS_ADDR          0x11100000 /* 01234 */
+#define AU1000_UART1_PHYS_ADDR          0x11200000 /* 0234 */
+#define AU1000_UART2_PHYS_ADDR          0x11300000 /* 0 */
+#define AU1000_UART3_PHYS_ADDR          0x11400000 /* 0123 */
+#define AU1500_GPIO2_PHYS_ADDR          0x11700000 /* 1234 */
+#define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
+#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 01234 */
+#define AU1000_DMA_PHYS_ADDR            0x14002000 /* 012 */
+#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 34 */
+#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 34 */
+#define AU1000_MACDMA0_PHYS_ADDR        0x14004000 /* 0123 */
+#define AU1000_MACDMA1_PHYS_ADDR        0x14004200 /* 0123 */
+
+
 #ifdef CONFIG_SOC_AU1000
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
-#define DMA0_PHYS_ADDR          0x14002000
-#define DMA1_PHYS_ADDR          0x14002100
-#define DMA2_PHYS_ADDR          0x14002200
-#define DMA3_PHYS_ADDR          0x14002300
-#define DMA4_PHYS_ADDR          0x14002400
-#define DMA5_PHYS_ADDR          0x14002500
-#define DMA6_PHYS_ADDR          0x14002600
-#define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
-#define AC97_PHYS_ADDR          0x10000000
 #define USBH_PHYS_ADDR          0x10100000
-#define USBD_PHYS_ADDR          0x10200000
 #define IRDA_PHYS_ADDR          0x10300000
-#define MAC0_PHYS_ADDR          0x10500000
-#define MAC1_PHYS_ADDR          0x10510000
-#define MACEN_PHYS_ADDR         0x10520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define I2S_PHYS_ADDR           0x11000000
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define UART2_PHYS_ADDR         0x11300000
-#define UART3_PHYS_ADDR         0x11400000
 #define SSI0_PHYS_ADDR          0x11600000
 #define SSI1_PHYS_ADDR          0x11680000
-#define SYS_PHYS_ADDR           0x11900000
 #define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
 #define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
 #define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
@@ -672,30 +729,8 @@ enum soc_au1200_ints {
 #ifdef CONFIG_SOC_AU1500
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
-#define DMA0_PHYS_ADDR          0x14002000
-#define DMA1_PHYS_ADDR          0x14002100
-#define DMA2_PHYS_ADDR          0x14002200
-#define DMA3_PHYS_ADDR          0x14002300
-#define DMA4_PHYS_ADDR          0x14002400
-#define DMA5_PHYS_ADDR          0x14002500
-#define DMA6_PHYS_ADDR          0x14002600
-#define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
-#define AC97_PHYS_ADDR          0x10000000
 #define USBH_PHYS_ADDR          0x10100000
-#define USBD_PHYS_ADDR          0x10200000
 #define PCI_PHYS_ADDR           0x14005000
-#define MAC0_PHYS_ADDR          0x11500000
-#define MAC1_PHYS_ADDR          0x11510000
-#define MACEN_PHYS_ADDR         0x11520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define I2S_PHYS_ADDR           0x11000000
-#define UART0_PHYS_ADDR         0x11100000
-#define UART3_PHYS_ADDR         0x11400000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
 #define PCI_MEM_PHYS_ADDR       0x400000000ULL
 #define PCI_IO_PHYS_ADDR        0x500000000ULL
 #define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
@@ -710,34 +745,10 @@ enum soc_au1200_ints {
 #ifdef CONFIG_SOC_AU1100
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
-#define DMA0_PHYS_ADDR          0x14002000
-#define DMA1_PHYS_ADDR          0x14002100
-#define DMA2_PHYS_ADDR          0x14002200
-#define DMA3_PHYS_ADDR          0x14002300
-#define DMA4_PHYS_ADDR          0x14002400
-#define DMA5_PHYS_ADDR          0x14002500
-#define DMA6_PHYS_ADDR          0x14002600
-#define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define SD0_PHYS_ADDR           0x10600000
-#define SD1_PHYS_ADDR           0x10680000
-#define IC1_PHYS_ADDR           0x11800000
-#define AC97_PHYS_ADDR          0x10000000
 #define USBH_PHYS_ADDR          0x10100000
-#define USBD_PHYS_ADDR          0x10200000
 #define IRDA_PHYS_ADDR          0x10300000
-#define MAC0_PHYS_ADDR          0x10500000
-#define MACEN_PHYS_ADDR         0x10520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define I2S_PHYS_ADDR           0x11000000
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define UART3_PHYS_ADDR         0x11400000
 #define SSI0_PHYS_ADDR          0x11600000
 #define SSI1_PHYS_ADDR          0x11680000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
 #define LCD_PHYS_ADDR           0x15000000
 #define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
 #define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
@@ -749,22 +760,8 @@ enum soc_au1200_ints {
 #ifdef CONFIG_SOC_AU1550
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
 #define USBH_PHYS_ADDR          0x14020000
-#define USBD_PHYS_ADDR          0x10200000
 #define PCI_PHYS_ADDR           0x14005000
-#define MAC0_PHYS_ADDR          0x10500000
-#define MAC1_PHYS_ADDR          0x10510000
-#define MACEN_PHYS_ADDR         0x10520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define UART3_PHYS_ADDR         0x11400000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
-#define DDMA_PHYS_ADDR          0x14002000
 #define PE_PHYS_ADDR            0x14008000
 #define PSC0_PHYS_ADDR          0x11A00000
 #define PSC1_PHYS_ADDR          0x11B00000
@@ -786,19 +783,10 @@ enum soc_au1200_ints {
 #define STATIC_MEM_PHYS_ADDR    0x14001000
 #define AES_PHYS_ADDR           0x10300000
 #define CIM_PHYS_ADDR           0x14004000
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
 #define USBM_PHYS_ADDR          0x14020000
 #define USBH_PHYS_ADDR          0x14020100
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
-#define DDMA_PHYS_ADDR          0x14002000
 #define PSC0_PHYS_ADDR          0x11A00000
 #define PSC1_PHYS_ADDR          0x11B00000
-#define SD0_PHYS_ADDR           0x10600000
-#define SD1_PHYS_ADDR           0x10680000
 #define LCD_PHYS_ADDR           0x15000000
 #define SWCNT_PHYS_ADDR         0x1110010C
 #define MAEFE_PHYS_ADDR         0x14012000
@@ -835,183 +823,43 @@ enum soc_au1200_ints {
 #endif
 
 
-/* Interrupt Controller register offsets */
-#define IC_CFG0RD               0x40
-#define IC_CFG0SET              0x40
-#define IC_CFG0CLR              0x44
-#define IC_CFG1RD               0x48
-#define IC_CFG1SET              0x48
-#define IC_CFG1CLR              0x4C
-#define IC_CFG2RD               0x50
-#define IC_CFG2SET              0x50
-#define IC_CFG2CLR              0x54
-#define IC_REQ0INT              0x54
-#define IC_SRCRD                0x58
-#define IC_SRCSET               0x58
-#define IC_SRCCLR               0x5C
-#define IC_REQ1INT              0x5C
-#define IC_ASSIGNRD             0x60
-#define IC_ASSIGNSET            0x60
-#define IC_ASSIGNCLR            0x64
-#define IC_WAKERD               0x68
-#define IC_WAKESET              0x68
-#define IC_WAKECLR              0x6C
-#define IC_MASKRD               0x70
-#define IC_MASKSET              0x70
-#define IC_MASKCLR              0x74
-#define IC_RISINGRD             0x78
-#define IC_RISINGCLR            0x78
-#define IC_FALLINGRD            0x7C
-#define IC_FALLINGCLR           0x7C
-#define IC_TESTBIT              0x80
-
-
-/* Interrupt Controller 0 */
-#define IC0_CFG0RD              0xB0400040
-#define IC0_CFG0SET             0xB0400040
-#define IC0_CFG0CLR             0xB0400044
-
-#define IC0_CFG1RD              0xB0400048
-#define IC0_CFG1SET             0xB0400048
-#define IC0_CFG1CLR             0xB040004C
-
-#define IC0_CFG2RD              0xB0400050
-#define IC0_CFG2SET             0xB0400050
-#define IC0_CFG2CLR             0xB0400054
-
-#define IC0_REQ0INT             0xB0400054
-#define IC0_SRCRD               0xB0400058
-#define IC0_SRCSET              0xB0400058
-#define IC0_SRCCLR              0xB040005C
-#define IC0_REQ1INT             0xB040005C
-
-#define IC0_ASSIGNRD            0xB0400060
-#define IC0_ASSIGNSET           0xB0400060
-#define IC0_ASSIGNCLR           0xB0400064
-
-#define IC0_WAKERD              0xB0400068
-#define IC0_WAKESET             0xB0400068
-#define IC0_WAKECLR             0xB040006C
-
-#define IC0_MASKRD              0xB0400070
-#define IC0_MASKSET             0xB0400070
-#define IC0_MASKCLR             0xB0400074
-
-#define IC0_RISINGRD            0xB0400078
-#define IC0_RISINGCLR           0xB0400078
-#define IC0_FALLINGRD           0xB040007C
-#define IC0_FALLINGCLR          0xB040007C
-
-#define IC0_TESTBIT             0xB0400080
-
-/* Interrupt Controller 1 */
-#define IC1_CFG0RD              0xB1800040
-#define IC1_CFG0SET             0xB1800040
-#define IC1_CFG0CLR             0xB1800044
-
-#define IC1_CFG1RD              0xB1800048
-#define IC1_CFG1SET             0xB1800048
-#define IC1_CFG1CLR             0xB180004C
-
-#define IC1_CFG2RD              0xB1800050
-#define IC1_CFG2SET             0xB1800050
-#define IC1_CFG2CLR             0xB1800054
-
-#define IC1_REQ0INT             0xB1800054
-#define IC1_SRCRD               0xB1800058
-#define IC1_SRCSET              0xB1800058
-#define IC1_SRCCLR              0xB180005C
-#define IC1_REQ1INT             0xB180005C
-
-#define IC1_ASSIGNRD            0xB1800060
-#define IC1_ASSIGNSET           0xB1800060
-#define IC1_ASSIGNCLR           0xB1800064
-
-#define IC1_WAKERD              0xB1800068
-#define IC1_WAKESET             0xB1800068
-#define IC1_WAKECLR             0xB180006C
-
-#define IC1_MASKRD              0xB1800070
-#define IC1_MASKSET             0xB1800070
-#define IC1_MASKCLR             0xB1800074
-
-#define IC1_RISINGRD            0xB1800078
-#define IC1_RISINGCLR           0xB1800078
-#define IC1_FALLINGRD           0xB180007C
-#define IC1_FALLINGCLR          0xB180007C
-
-#define IC1_TESTBIT             0xB1800080
 
 
 /* Au1000 */
 #ifdef CONFIG_SOC_AU1000
 
-#define UART0_ADDR              0xB1100000
-#define UART3_ADDR              0xB1400000
-
 #define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
 #define USB_HOST_CONFIG         0xB017FFFC
 #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
-
-#define AU1000_ETH0_BASE        0xB0500000
-#define AU1000_ETH1_BASE        0xB0510000
-#define AU1000_MAC0_ENABLE      0xB0520000
-#define AU1000_MAC1_ENABLE      0xB0520004
-#define NUM_ETH_INTERFACES 2
 #endif /* CONFIG_SOC_AU1000 */
 
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
 
-#define UART0_ADDR              0xB1100000
-#define UART3_ADDR              0xB1400000
-
 #define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
 #define USB_HOST_CONFIG         0xB017fffc
 #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
-
-#define AU1500_ETH0_BASE        0xB1500000
-#define AU1500_ETH1_BASE        0xB1510000
-#define AU1500_MAC0_ENABLE      0xB1520000
-#define AU1500_MAC1_ENABLE      0xB1520004
-#define NUM_ETH_INTERFACES 2
 #endif /* CONFIG_SOC_AU1500 */
 
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
 
-#define UART0_ADDR              0xB1100000
-#define UART3_ADDR              0xB1400000
-
 #define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
 #define USB_HOST_CONFIG         0xB017FFFC
 #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
-
-#define AU1100_ETH0_BASE        0xB0500000
-#define AU1100_MAC0_ENABLE      0xB0520000
-#define NUM_ETH_INTERFACES 1
 #endif /* CONFIG_SOC_AU1100 */
 
 #ifdef CONFIG_SOC_AU1550
-#define UART0_ADDR              0xB1100000
 
 #define USB_OHCI_BASE           0x14020000      /* phys addr for ioremap */
 #define USB_OHCI_LEN            0x00060000
 #define USB_HOST_CONFIG         0xB4027ffc
 #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
-
-#define AU1550_ETH0_BASE        0xB0500000
-#define AU1550_ETH1_BASE        0xB0510000
-#define AU1550_MAC0_ENABLE      0xB0520000
-#define AU1550_MAC1_ENABLE      0xB0520004
-#define NUM_ETH_INTERFACES 2
 #endif /* CONFIG_SOC_AU1550 */
 
 
 #ifdef CONFIG_SOC_AU1200
 
-#define UART0_ADDR              0xB1100000
-
 #define USB_UOC_BASE            0x14020020
 #define USB_UOC_LEN             0x20
 #define USB_OHCI_BASE           0x14020100
@@ -1504,22 +1352,6 @@ enum soc_au1200_ints {
 #define SYS_PINFUNC_S1B         (1 << 2)
 #endif
 
-#define SYS_TRIOUTRD            0xB1900100
-#define SYS_TRIOUTCLR           0xB1900100
-#define SYS_OUTPUTRD            0xB1900108
-#define SYS_OUTPUTSET           0xB1900108
-#define SYS_OUTPUTCLR           0xB190010C
-#define SYS_PINSTATERD          0xB1900110
-#define SYS_PININPUTEN          0xB1900110
-
-/* GPIO2, Au1500, Au1550 only */
-#define GPIO2_BASE              0xB1700000
-#define GPIO2_DIR               (GPIO2_BASE + 0)
-#define GPIO2_OUTPUT            (GPIO2_BASE + 8)
-#define GPIO2_PINSTATE          (GPIO2_BASE + 0xC)
-#define GPIO2_INTENABLE         (GPIO2_BASE + 0x10)
-#define GPIO2_ENABLE            (GPIO2_BASE + 0x14)
-
 /* Power Management */
 #define SYS_SCRATCH0            0xB1900018
 #define SYS_SCRATCH1            0xB190001C
@@ -1635,12 +1467,6 @@ enum soc_au1200_ints {
 #  define AC97C_RS              (1 << 1)
 #  define AC97C_CE              (1 << 0)
 
-/* Secure Digital (SD) Controller */
-#define SD0_XMIT_FIFO   0xB0600000
-#define SD0_RECV_FIFO   0xB0600004
-#define SD1_XMIT_FIFO   0xB0680000
-#define SD1_RECV_FIFO   0xB0680004
-
 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
 /* Au1500 PCI Controller */
 #define Au1500_CFG_BASE         0xB4005000      /* virtual, KSEG1 addr */