1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 2de638f84c86..43baed16a109 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -42,7 +42,7 @@ ASMMACRO(_ehb,
 /*
 * TLB hazards
 */
-#if defined(CONFIG_CPU_MIPSR2)
+#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
 /*
 * MIPSR2 defines ehb for hazard avoidance
@@ -138,7 +138,7 @@ do {									\
                __instruction_hazard();                                 \
 } while (0)
-#elif defined(CONFIG_CPU_R10000)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
 /*
 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.

diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 2de638f84c86..43baed16a109 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h
@@ -42,7 +42,7 @@ ASMMACRO(_ehb,
42	/*	42	/*
43	* TLB hazards	43	* TLB hazards
44	*/	44	*/
45	#if defined(CONFIG_CPU_MIPSR2)	45	#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
46		46
47	/*	47	/*
48	* MIPSR2 defines ehb for hazard avoidance	48	* MIPSR2 defines ehb for hazard avoidance
@@ -138,7 +138,7 @@ do { \
138	__instruction_hazard(); \	138	__instruction_hazard(); \
139	} while (0)	139	} while (0)
140		140
141	#elif defined(CONFIG_CPU_R10000)	141	#elif defined(CONFIG_CPU_R10000) \|\| defined(CONFIG_CPU_CAVIUM_OCTEON)
142		142
143	/*	143	/*
144	* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.	144	* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.