diff options
Diffstat (limited to 'arch/mips/include/asm/gcmpregs.h')
| -rw-r--r-- | arch/mips/include/asm/gcmpregs.h | 100 |
1 files changed, 50 insertions, 50 deletions
diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h index c0cf76a2ca89..a7359f77a48e 100644 --- a/arch/mips/include/asm/gcmpregs.h +++ b/arch/mips/include/asm/gcmpregs.h | |||
| @@ -32,7 +32,7 @@ | |||
| 32 | 32 | ||
| 33 | /* GCMP register access */ | 33 | /* GCMP register access */ |
| 34 | #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) | 34 | #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) |
| 35 | #define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n)) | 35 | #define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n)) |
| 36 | #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) | 36 | #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) |
| 37 | #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) | 37 | #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) |
| 38 | #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) | 38 | #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) |
| @@ -45,76 +45,76 @@ | |||
| 45 | 45 | ||
| 46 | /* GCB registers */ | 46 | /* GCB registers */ |
| 47 | #define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */ | 47 | #define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */ |
| 48 | #define GCMP_GCB_GC_NUMIOCU_SHF 8 | 48 | #define GCMP_GCB_GC_NUMIOCU_SHF 8 |
| 49 | #define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4) | 49 | #define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4) |
| 50 | #define GCMP_GCB_GC_NUMCORES_SHF 0 | 50 | #define GCMP_GCB_GC_NUMCORES_SHF 0 |
| 51 | #define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8) | 51 | #define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8) |
| 52 | #define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */ | 52 | #define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */ |
| 53 | #define GCMP_GCB_GCMPB_GCMPBASE_SHF 15 | 53 | #define GCMP_GCB_GCMPB_GCMPBASE_SHF 15 |
| 54 | #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) | 54 | #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) |
| 55 | #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 | 55 | #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 |
| 56 | #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) | 56 | #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) |
| 57 | #define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0 | 57 | #define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0 |
| 58 | #define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1 | 58 | #define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1 |
| 59 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 | 59 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 |
| 60 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 | 60 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 |
| 61 | #define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ | 61 | #define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ |
| 62 | #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ | 62 | #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ |
| 63 | #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 | 63 | #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 |
| 64 | #define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8) | 64 | #define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8) |
| 65 | #define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */ | 65 | #define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */ |
| 66 | #define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */ | 66 | #define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */ |
| 67 | #define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */ | 67 | #define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */ |
| 68 | #define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27 | 68 | #define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27 |
| 69 | #define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5) | 69 | #define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5) |
| 70 | #define GCMP_GCB_GMEC_ERROR_INFO_SHF 0 | 70 | #define GCMP_GCB_GMEC_ERROR_INFO_SHF 0 |
| 71 | #define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27) | 71 | #define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27) |
| 72 | #define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */ | 72 | #define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */ |
| 73 | #define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */ | 73 | #define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */ |
| 74 | #define GCMP_GCB_GMEO_ERROR_2ND_SHF 0 | 74 | #define GCMP_GCB_GMEO_ERROR_2ND_SHF 0 |
| 75 | #define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5) | 75 | #define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5) |
| 76 | #define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ | 76 | #define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ |
| 77 | #define GCMP_GCB_GICBA_BASE_SHF 17 | 77 | #define GCMP_GCB_GICBA_BASE_SHF 17 |
| 78 | #define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15) | 78 | #define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15) |
| 79 | #define GCMP_GCB_GICBA_EN_SHF 0 | 79 | #define GCMP_GCB_GICBA_EN_SHF 0 |
| 80 | #define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1) | 80 | #define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1) |
| 81 | 81 | ||
| 82 | /* GCB Regions */ | 82 | /* GCB Regions */ |
| 83 | #define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */ | 83 | #define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */ |
| 84 | #define GCMP_GCB_CMxBASE_BASE_SHF 16 | 84 | #define GCMP_GCB_CMxBASE_BASE_SHF 16 |
| 85 | #define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16) | 85 | #define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16) |
| 86 | #define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */ | 86 | #define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */ |
| 87 | #define GCMP_GCB_CMxMASK_MASK_SHF 16 | 87 | #define GCMP_GCB_CMxMASK_MASK_SHF 16 |
| 88 | #define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16) | 88 | #define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16) |
| 89 | #define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0 | 89 | #define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0 |
| 90 | #define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2) | 90 | #define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2) |
| 91 | #define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0 | 91 | #define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0 |
| 92 | #define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1 | 92 | #define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1 |
| 93 | #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2 | 93 | #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2 |
| 94 | #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3 | 94 | #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3 |
| 95 | 95 | ||
| 96 | 96 | ||
| 97 | /* Core local/Core other control block registers */ | 97 | /* Core local/Core other control block registers */ |
| 98 | #define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */ | 98 | #define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */ |
| 99 | #define GCMP_CCB_RESETR_INRESET_SHF 0 | 99 | #define GCMP_CCB_RESETR_INRESET_SHF 0 |
| 100 | #define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16) | 100 | #define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16) |
| 101 | #define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */ | 101 | #define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */ |
| 102 | #define GCMP_CCB_COHCTL_DOMAIN_SHF 0 | 102 | #define GCMP_CCB_COHCTL_DOMAIN_SHF 0 |
| 103 | #define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8) | 103 | #define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8) |
| 104 | #define GCMP_CCB_CFG_OFS 0x0010 /* Config */ | 104 | #define GCMP_CCB_CFG_OFS 0x0010 /* Config */ |
| 105 | #define GCMP_CCB_CFG_IOCUTYPE_SHF 10 | 105 | #define GCMP_CCB_CFG_IOCUTYPE_SHF 10 |
| 106 | #define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2) | 106 | #define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2) |
| 107 | #define GCMP_CCB_CFG_IOCUTYPE_CPU 0 | 107 | #define GCMP_CCB_CFG_IOCUTYPE_CPU 0 |
| 108 | #define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1 | 108 | #define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1 |
| 109 | #define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2 | 109 | #define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2 |
| 110 | #define GCMP_CCB_CFG_NUMVPE_SHF 0 | 110 | #define GCMP_CCB_CFG_NUMVPE_SHF 0 |
| 111 | #define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10) | 111 | #define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10) |
| 112 | #define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */ | 112 | #define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */ |
| 113 | #define GCMP_CCB_OTHER_CORENUM_SHF 16 | 113 | #define GCMP_CCB_OTHER_CORENUM_SHF 16 |
| 114 | #define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16) | 114 | #define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16) |
| 115 | #define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */ | 115 | #define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */ |
| 116 | #define GCMP_CCB_RESETBASE_BEV_SHF 12 | 116 | #define GCMP_CCB_RESETBASE_BEV_SHF 12 |
| 117 | #define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20) | 117 | #define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20) |
| 118 | #define GCMP_CCB_ID_OFS 0x0028 /* Identification */ | 118 | #define GCMP_CCB_ID_OFS 0x0028 /* Identification */ |
| 119 | #define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */ | 119 | #define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */ |
| 120 | #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ | 120 | #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ |