1 files changed, 12 insertions, 12 deletions
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index ef9987a61d88..1de190bdfb9c 100644
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -45,19 +45,19 @@
                "       "__UA_ADDR "\t2b, 4b                    \n"     \
                "       .previous                               \n"     \
                : "=r" (ret), "=&r" (oldval),                           \
-                  "=" GCC_OFF12_ASM() (*uaddr)                          \
+                  "=" GCC_OFF_SMALL_ASM() (*uaddr)                              \
-                : "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg),      \
+                : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg),  \
                  "i" (-EFAULT)                                         \
                : "memory");                                            \
        } else if (cpu_has_llsc) {                                      \
                __asm__ __volatile__(                                   \
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
-                "       .set    arch=r4000                      \n"     \
+                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"     \
                "1:     "user_ll("%1", "%4")" # __futex_atomic_op\n"    \
                "       .set    mips0                           \n"     \
                "       " insn  "                               \n"     \
-                "       .set    arch=r4000                      \n"     \
+                "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"     \
                "2:     "user_sc("$1", "%2")"                   \n"     \
                "       beqz    $1, 1b                          \n"     \
                __WEAK_LLSC_MB                                          \
@@ -74,8 +74,8 @@
                "       "__UA_ADDR "\t2b, 4b                    \n"     \
                "       .previous                               \n"     \
                : "=r" (ret), "=&r" (oldval),                           \
-                  "=" GCC_OFF12_ASM() (*uaddr)                          \
+                  "=" GCC_OFF_SMALL_ASM() (*uaddr)                              \
-                : "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg),      \
+                : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg),  \
                  "i" (-EFAULT)                                         \
                : "memory");                                            \
        } else                                                          \
@@ -174,8 +174,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                "       "__UA_ADDR "\t1b, 4b                            \n"
                "       "__UA_ADDR "\t2b, 4b                            \n"
                "       .previous                                       \n"
-                : "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)
+                : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
-                : GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
+                : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
                  "i" (-EFAULT)
                : "memory");
        } else if (cpu_has_llsc) {
@@ -183,12 +183,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                "# futex_atomic_cmpxchg_inatomic                        \n"
                "       .set    push                                    \n"
                "       .set    noat                                    \n"
-                "       .set    arch=r4000                              \n"
+                "       .set    "MIPS_ISA_ARCH_LEVEL"                   \n"
                "1:     "user_ll("%1", "%3")"                           \n"
                "       bne     %1, %z4, 3f                             \n"
                "       .set    mips0                                   \n"
                "       move    $1, %z5                                 \n"
-                "       .set    arch=r4000                              \n"
+                "       .set    "MIPS_ISA_ARCH_LEVEL"                   \n"
                "2:     "user_sc("$1", "%2")"                           \n"
                "       beqz    $1, 1b                                  \n"
                __WEAK_LLSC_MB
@@ -203,8 +203,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                "       "__UA_ADDR "\t1b, 4b                            \n"
                "       "__UA_ADDR "\t2b, 4b                            \n"
                "       .previous                                       \n"
-                : "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)
+                : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
-                : GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
+                : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
                  "i" (-EFAULT)
                : "memory");
        } else

diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h index ef9987a61d88..1de190bdfb9c 100644 --- a/arch/mips/include/asm/futex.h +++ b/arch/mips/include/asm/futex.h
@@ -45,19 +45,19 @@
45	" "__UA_ADDR "\t2b, 4b \n" \	45	" "__UA_ADDR "\t2b, 4b \n" \
46	" .previous \n" \	46	" .previous \n" \
47	: "=r" (ret), "=&r" (oldval), \	47	: "=r" (ret), "=&r" (oldval), \
48	"=" GCC_OFF12_ASM() (*uaddr) \	48	"=" GCC_OFF_SMALL_ASM() (*uaddr) \
49	: "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \	49	: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
50	"i" (-EFAULT) \	50	"i" (-EFAULT) \
51	: "memory"); \	51	: "memory"); \
52	} else if (cpu_has_llsc) { \	52	} else if (cpu_has_llsc) { \
53	__asm__ __volatile__( \	53	__asm__ __volatile__( \
54	" .set push \n" \	54	" .set push \n" \
55	" .set noat \n" \	55	" .set noat \n" \
56	" .set arch=r4000 \n" \	56	" .set "MIPS_ISA_ARCH_LEVEL" \n" \
57	"1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \	57	"1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
58	" .set mips0 \n" \	58	" .set mips0 \n" \
59	" " insn " \n" \	59	" " insn " \n" \
60	" .set arch=r4000 \n" \	60	" .set "MIPS_ISA_ARCH_LEVEL" \n" \
61	"2: "user_sc("$1", "%2")" \n" \	61	"2: "user_sc("$1", "%2")" \n" \
62	" beqz $1, 1b \n" \	62	" beqz $1, 1b \n" \
63	__WEAK_LLSC_MB \	63	__WEAK_LLSC_MB \
@@ -74,8 +74,8 @@
74	" "__UA_ADDR "\t2b, 4b \n" \	74	" "__UA_ADDR "\t2b, 4b \n" \
75	" .previous \n" \	75	" .previous \n" \
76	: "=r" (ret), "=&r" (oldval), \	76	: "=r" (ret), "=&r" (oldval), \
77	"=" GCC_OFF12_ASM() (*uaddr) \	77	"=" GCC_OFF_SMALL_ASM() (*uaddr) \
78	: "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \	78	: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
79	"i" (-EFAULT) \	79	"i" (-EFAULT) \
80	: "memory"); \	80	: "memory"); \
81	} else \	81	} else \
@@ -174,8 +174,8 @@ futex_atomic_cmpxchg_inatomic(u32 uval, u32 __user uaddr,
174	" "__UA_ADDR "\t1b, 4b \n"	174	" "__UA_ADDR "\t1b, 4b \n"
175	" "__UA_ADDR "\t2b, 4b \n"	175	" "__UA_ADDR "\t2b, 4b \n"
176	" .previous \n"	176	" .previous \n"
177	: "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)	177	: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
178	: GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),	178	: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
179	"i" (-EFAULT)	179	"i" (-EFAULT)
180	: "memory");	180	: "memory");
181	} else if (cpu_has_llsc) {	181	} else if (cpu_has_llsc) {
@@ -183,12 +183,12 @@ futex_atomic_cmpxchg_inatomic(u32 uval, u32 __user uaddr,
183	"# futex_atomic_cmpxchg_inatomic \n"	183	"# futex_atomic_cmpxchg_inatomic \n"
184	" .set push \n"	184	" .set push \n"
185	" .set noat \n"	185	" .set noat \n"
186	" .set arch=r4000 \n"	186	" .set "MIPS_ISA_ARCH_LEVEL" \n"
187	"1: "user_ll("%1", "%3")" \n"	187	"1: "user_ll("%1", "%3")" \n"
188	" bne %1, %z4, 3f \n"	188	" bne %1, %z4, 3f \n"
189	" .set mips0 \n"	189	" .set mips0 \n"
190	" move $1, %z5 \n"	190	" move $1, %z5 \n"
191	" .set arch=r4000 \n"	191	" .set "MIPS_ISA_ARCH_LEVEL" \n"
192	"2: "user_sc("$1", "%2")" \n"	192	"2: "user_sc("$1", "%2")" \n"
193	" beqz $1, 1b \n"	193	" beqz $1, 1b \n"
194	__WEAK_LLSC_MB	194	__WEAK_LLSC_MB
@@ -203,8 +203,8 @@ futex_atomic_cmpxchg_inatomic(u32 uval, u32 __user uaddr,
203	" "__UA_ADDR "\t1b, 4b \n"	203	" "__UA_ADDR "\t1b, 4b \n"
204	" "__UA_ADDR "\t2b, 4b \n"	204	" "__UA_ADDR "\t2b, 4b \n"
205	" .previous \n"	205	" .previous \n"
206	: "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)	206	: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
207	: GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),	207	: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
208	"i" (-EFAULT)	208	"i" (-EFAULT)
209	: "memory");	209	: "memory");
210	} else	210	} else