1 files changed, 10 insertions, 5 deletions

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 76411df3d971..530eb8b3a68e 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -82,10 +82,10 @@
 #define PRID_IMP_RM7000         0x2700
 #define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
 #define PRID_IMP_RM9000         0x3400
-#define PRID_IMP_LOONGSON1      0x4200
+#define PRID_IMP_LOONGSON_32    0x4200  /* Loongson-1 */
 #define PRID_IMP_R5432          0x5400
 #define PRID_IMP_R5500          0x5500
-#define PRID_IMP_LOONGSON2      0x6300
+#define PRID_IMP_LOONGSON_64    0x6300  /* Loongson-2/3 */
 
 #define PRID_IMP_UNKNOWN        0xff00
 
@@ -115,6 +115,8 @@
 #define PRID_IMP_INTERAPTIV_MP  0xa100
 #define PRID_IMP_PROAPTIV_UP    0xa200
 #define PRID_IMP_PROAPTIV_MP    0xa300
+#define PRID_IMP_M5150          0xa700
+#define PRID_IMP_P5600          0xa800
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -229,6 +231,7 @@
 #define PRID_REV_LOONGSON1B     0x0020
 #define PRID_REV_LOONGSON2E     0x0002
 #define PRID_REV_LOONGSON2F     0x0003
+#define PRID_REV_LOONGSON3A     0x0005
 
 /*
  * Older processors used to encode processor version and revision in two
@@ -296,14 +299,14 @@ enum cpu_type_enum {
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
         CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
         CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
-        CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,
+        CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
 
         /*
          * MIPS64 class processors
          */
         CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-        CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
-        CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
+        CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+        CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
 
         CPU_LAST
 };
@@ -358,6 +361,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_MICROMIPS      0x01000000 /* CPU has microMIPS capability */
 #define MIPS_CPU_TLBINV         0x02000000 /* CPU supports TLBINV/F */
 #define MIPS_CPU_SEGMENTS       0x04000000 /* CPU supports Segmentation Control registers */
+#define MIPS_CPU_EVA            0x80000000 /* CPU supports Enhanced Virtual Addressing */
 
 /*
  * CPU ASE encodings
@@ -370,5 +374,6 @@ enum cpu_type_enum {
 #define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
 #define MIPS_ASE_DSP2P          0x00000040 /* Signal Processing ASE Rev 2 */
 #define MIPS_ASE_VZ             0x00000080 /* Virtualization ASE */
+#define MIPS_ASE_MSA            0x00000100 /* MIPS SIMD Architecture */
 
 #endif /* _ASM_CPU_H */