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-rw-r--r--arch/mips/include/asm/cpu.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index d2035e16502a..76411df3d971 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -111,6 +111,10 @@
111#define PRID_IMP_1074K 0x9a00 111#define PRID_IMP_1074K 0x9a00
112#define PRID_IMP_M14KC 0x9c00 112#define PRID_IMP_M14KC 0x9c00
113#define PRID_IMP_M14KEC 0x9e00 113#define PRID_IMP_M14KEC 0x9e00
114#define PRID_IMP_INTERAPTIV_UP 0xa000
115#define PRID_IMP_INTERAPTIV_MP 0xa100
116#define PRID_IMP_PROAPTIV_UP 0xa200
117#define PRID_IMP_PROAPTIV_MP 0xa300
114 118
115/* 119/*
116 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 120 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -194,6 +198,7 @@
194#define PRID_IMP_NETLOGIC_XLP8XX 0x1000 198#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
195#define PRID_IMP_NETLOGIC_XLP3XX 0x1100 199#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
196#define PRID_IMP_NETLOGIC_XLP2XX 0x1200 200#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
201#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
197 202
198/* 203/*
199 * Particular Revision values for bits 7:0 of the PRId register. 204 * Particular Revision values for bits 7:0 of the PRId register.
@@ -249,6 +254,8 @@
249 254
250#define FPIR_IMP_NONE 0x0000 255#define FPIR_IMP_NONE 0x0000
251 256
257#if !defined(__ASSEMBLY__)
258
252enum cpu_type_enum { 259enum cpu_type_enum {
253 CPU_UNKNOWN, 260 CPU_UNKNOWN,
254 261
@@ -289,7 +296,7 @@ enum cpu_type_enum {
289 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 296 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
290 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 297 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
291 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 298 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
292 CPU_M14KEC, 299 CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,
293 300
294 /* 301 /*
295 * MIPS64 class processors 302 * MIPS64 class processors
@@ -301,6 +308,7 @@ enum cpu_type_enum {
301 CPU_LAST 308 CPU_LAST
302}; 309};
303 310
311#endif /* !__ASSEMBLY */
304 312
305/* 313/*
306 * ISA Level encodings 314 * ISA Level encodings
@@ -348,6 +356,8 @@ enum cpu_type_enum {
348#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 356#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
349#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 357#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
350#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ 358#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
359#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */
360#define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */
351 361
352/* 362/*
353 * CPU ASE encodings 363 * CPU ASE encodings