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-rw-r--r--arch/mips/include/asm/cpu-features.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c0047f861337..8ab1d12ba7f4 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -147,6 +147,10 @@
147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
148 cpu_has_mips64r1 | cpu_has_mips64r2) 148 cpu_has_mips64r1 | cpu_has_mips64r2)
149 149
150#ifndef cpu_has_mips_r2_exec_hazard
151#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
152#endif
153
150/* 154/*
151 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 155 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
152 * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels 156 * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
@@ -230,4 +234,8 @@
230#define cpu_scache_line_size() cpu_data[0].scache.linesz 234#define cpu_scache_line_size() cpu_data[0].scache.linesz
231#endif 235#endif
232 236
237#ifndef cpu_hwrena_impl_bits
238#define cpu_hwrena_impl_bits 0
239#endif
240
233#endif /* __ASM_CPU_FEATURES_H */ 241#endif /* __ASM_CPU_FEATURES_H */