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-rw-r--r--arch/mips/gt64120/common/Makefile6
-rw-r--r--arch/mips/gt64120/common/pci.c147
-rw-r--r--arch/mips/gt64120/common/time.c100
-rw-r--r--arch/mips/gt64120/ev64120/Makefile11
-rw-r--r--arch/mips/gt64120/ev64120/int-handler.S113
-rw-r--r--arch/mips/gt64120/ev64120/irq.c145
-rw-r--r--arch/mips/gt64120/ev64120/promcon.c53
-rw-r--r--arch/mips/gt64120/ev64120/reset.c45
-rw-r--r--arch/mips/gt64120/ev64120/serialGT.c212
-rw-r--r--arch/mips/gt64120/ev64120/setup.c103
-rw-r--r--arch/mips/gt64120/momenco_ocelot/Makefile9
-rw-r--r--arch/mips/gt64120/momenco_ocelot/dbg_io.c126
-rw-r--r--arch/mips/gt64120/momenco_ocelot/int-handler.S131
-rw-r--r--arch/mips/gt64120/momenco_ocelot/irq.c67
-rw-r--r--arch/mips/gt64120/momenco_ocelot/ocelot_pld.h30
-rw-r--r--arch/mips/gt64120/momenco_ocelot/prom.c73
-rw-r--r--arch/mips/gt64120/momenco_ocelot/reset.c47
-rw-r--r--arch/mips/gt64120/momenco_ocelot/setup.c369
18 files changed, 1787 insertions, 0 deletions
diff --git a/arch/mips/gt64120/common/Makefile b/arch/mips/gt64120/common/Makefile
new file mode 100644
index 000000000000..eba5051015a5
--- /dev/null
+++ b/arch/mips/gt64120/common/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for common code of gt64120-based boards.
3#
4
5obj-y += time.o
6obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/gt64120/common/pci.c b/arch/mips/gt64120/common/pci.c
new file mode 100644
index 000000000000..e9e5419a0d53
--- /dev/null
+++ b/arch/mips/gt64120/common/pci.c
@@ -0,0 +1,147 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Galileo Evaluation Boards PCI support.
4 *
5 * The general-purpose functions to read/write and configure the GT64120A's
6 * PCI registers (function names start with pci0 or pci1) are either direct
7 * copies of functions written by Galileo Technology, or are modifications
8 * of their functions to work with Linux 2.4 vs Linux 2.2. These functions
9 * are Copyright - Galileo Technology.
10 *
11 * Other functions are derived from other MIPS PCI implementations, or were
12 * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/init.h>
36#include <linux/types.h>
37#include <linux/pci.h>
38#include <linux/kernel.h>
39#include <asm/gt64120.h>
40
41#define SELF 0
42
43/*
44 * pciXReadConfigReg - Read from a PCI configuration register
45 * - Make sure the GT is configured as a master before
46 * reading from another device on the PCI.
47 * - The function takes care of Big/Little endian conversion.
48 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
49 * spec)
50 * pciDevNum: The device number needs to be addressed.
51 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
52 * cause register to make sure the data is valid
53 *
54 * Configuration Address 0xCF8:
55 *
56 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
57 * |congif|Reserved| Bus |Device|Function|Register|00|
58 * |Enable| |Number|Number| Number | Number | | <=field Name
59 *
60 */
61static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device)
62{
63 unsigned int DataForRegCf8;
64 unsigned int data;
65
66 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
67 (PCI_FUNC(device->devfn) << 8) |
68 (offset & ~0x3)) | 0x80000000;
69 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
70
71 /*
72 * The casual observer might wonder why the READ is duplicated here,
73 * rather than immediately following the WRITE, and just have the swap
74 * in the "if". That's because there is a latency problem with trying
75 * to read immediately after setting up the address register. The "if"
76 * check gives enough time for the address to stabilize, so the READ
77 * can work.
78 */
79 if (PCI_SLOT(device->devfn) == SELF) /* This board */
80 return GT_READ(GT_PCI0_CFGDATA_OFS);
81 else /* PCI is little endian so swap the Data. */
82 return __GT_READ(GT_PCI0_CFGDATA_OFS);
83}
84
85/*
86 * pciXWriteConfigReg - Write to a PCI configuration register
87 * - Make sure the GT is configured as a master before
88 * writingto another device on the PCI.
89 * - The function takes care of Big/Little endian conversion.
90 * Inputs: unsigned int regOffset: The register offset as it apears in the
91 * GT spec
92 * (or any other PCI device spec)
93 * pciDevNum: The device number needs to be addressed.
94 *
95 * Configuration Address 0xCF8:
96 *
97 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
98 * |congif|Reserved| Bus |Device|Function|Register|00|
99 * |Enable| |Number|Number| Number | Number | | <=field Name
100 *
101 */
102static void pci0WriteConfigReg(unsigned int offset,
103 struct pci_dev *device, unsigned int data)
104{
105 unsigned int DataForRegCf8;
106
107 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
108 (PCI_FUNC(device->devfn) << 8) |
109 (offset & ~0x3)) | 0x80000000;
110 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
111
112 if (PCI_SLOT(device->devfn) == SELF) /* This board */
113 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
114 else /* configuration Transaction over the pci. */
115 __GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
116}
117
118extern struct pci_ops gt64120_pci_ops;
119
120void __init pcibios_init(void)
121{
122 u32 tmp;
123 struct pci_dev controller;
124
125 controller.devfn = SELF;
126
127 tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
128 tmp = GT_READ(GT_PCI0_BARE_OFS);
129
130 /*
131 * You have to enable bus mastering to configure any other
132 * card on the bus.
133 */
134 tmp = pci0ReadConfigReg(PCI_COMMAND, &controller);
135 tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
136 pci0WriteConfigReg(PCI_COMMAND, &controller, tmp);
137
138 /*
139 * Reset PCI I/O and PCI MEM values to ones supported by EVM.
140 */
141 ioport_resource.start = GT_PCI_IO_BASE;
142 ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
143 iomem_resource.start = GT_PCI_MEM_BASE;
144 iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1;
145
146 pci_scan_bus(0, &gt64120_pci_ops, NULL);
147}
diff --git a/arch/mips/gt64120/common/time.c b/arch/mips/gt64120/common/time.c
new file mode 100644
index 000000000000..2287b59536e5
--- /dev/null
+++ b/arch/mips/gt64120/common/time.c
@@ -0,0 +1,100 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Galileo Technology chip interrupt handler
8 */
9#include <linux/interrupt.h>
10#include <linux/kernel.h>
11#include <linux/config.h>
12#include <linux/sched.h>
13#include <linux/kernel_stat.h>
14#include <asm/ptrace.h>
15#include <asm/gt64120.h>
16
17/*
18 * These are interrupt handlers for the GT on-chip interrupts. They all come
19 * in to the MIPS on a single interrupt line, and have to be handled and ack'ed
20 * differently than other MIPS interrupts.
21 */
22
23static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs)
24{
25 unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;
26 int handled = 0;
27
28 irq_src = GT_READ(GT_INTRCAUSE_OFS);
29 irq_src_mask = GT_READ(GT_INTRMASK_OFS);
30 int_high_src = GT_READ(GT_HINTRCAUSE_OFS);
31 int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);
32 irq_src = irq_src & irq_src_mask;
33 int_high_src = int_high_src & int_high_src_mask;
34
35 if (irq_src & 0x00000800) { /* Check for timer interrupt */
36 handled = 1;
37 irq_src &= ~0x00000800;
38 do_timer(regs);
39#ifndef CONFIG_SMP
40 update_process_times(user_mode(regs));
41#endif
42 }
43
44 GT_WRITE(GT_INTRCAUSE_OFS, 0);
45 GT_WRITE(GT_HINTRCAUSE_OFS, 0);
46}
47
48/*
49 * Initializes timer using galileo's built in timer.
50 */
51#ifdef CONFIG_SYSCLK_100
52#define Sys_clock (100 * 1000000) // 100 MHz
53#endif
54#ifdef CONFIG_SYSCLK_83
55#define Sys_clock (83.333 * 1000000) // 83.333 MHz
56#endif
57#ifdef CONFIG_SYSCLK_75
58#define Sys_clock (75 * 1000000) // 75 MHz
59#endif
60
61/*
62 * This will ignore the standard MIPS timer interrupt handler that is passed in
63 * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt
64 * handling.
65 */
66void gt64120_time_init(void)
67{
68 static struct irqaction timer;
69
70 /* Disable timer first */
71 GT_WRITE(GT_TC_CONTROL_OFS, 0);
72 /* Load timer value for 100 Hz */
73 GT_WRITE(GT_TC3_OFS, Sys_clock / 100);
74
75 /*
76 * Create the IRQ structure entry for the timer. Since we're too early
77 * in the boot process to use the "request_irq()" call, we'll hard-code
78 * the values to the correct interrupt line.
79 */
80 timer.handler = gt64120_irq;
81 timer.flags = SA_SHIRQ | SA_INTERRUPT;
82 timer.name = "timer";
83 timer.dev_id = NULL;
84 timer.next = NULL;
85 timer.mask = CPU_MASK_NONE;
86 irq_desc[GT_TIMER].action = &timer;
87
88 enable_irq(GT_TIMER);
89
90 /* Enable timer ints */
91 GT_WRITE(GT_TC_CONTROL_OFS, 0xc0);
92 /* clear Cause register first */
93 GT_WRITE(GT_INTRCAUSE_OFS, 0x0);
94 /* Unmask timer int */
95 GT_WRITE(GT_INTRMASK_OFS, 0x800);
96 /* Clear High int register */
97 GT_WRITE(GT_HINTRCAUSE_OFS, 0x0);
98 /* Mask All interrupts at High cause interrupt */
99 GT_WRITE(GT_HINTRMASK_OFS, 0x0);
100}
diff --git a/arch/mips/gt64120/ev64120/Makefile b/arch/mips/gt64120/ev64120/Makefile
new file mode 100644
index 000000000000..ebe91c57e173
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/Makefile
@@ -0,0 +1,11 @@
1#
2# Copyright 2000 RidgeRun, Inc.
3# Author: RidgeRun, Inc.
4# glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5#
6# Makefile for the Galileo EV64120 board.
7#
8
9obj-y += int-handler.o irq.o promcon.o reset.o serialGT.o setup.o
10
11EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/gt64120/ev64120/int-handler.S b/arch/mips/gt64120/ev64120/int-handler.S
new file mode 100644
index 000000000000..752435faf2de
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/int-handler.S
@@ -0,0 +1,113 @@
1/*
2 * int-handler.S
3 *
4 * Based on the cobalt handler.
5 */
6#include <asm/asm.h>
7#include <asm/mipsregs.h>
8#include <asm/addrspace.h>
9#include <asm/regdef.h>
10#include <asm/stackframe.h>
11
12/*
13 * galileo_handle_int -
14 * We check for the timer first, then check PCI ints A and D.
15 * Then check for serial IRQ and fall through.
16 */
17 .align 5
18 .set reorder
19 .set noat
20 NESTED(galileo_handle_int, PT_SIZE, sp)
21 SAVE_ALL
22 CLI
23 .set at
24 mfc0 t0,CP0_CAUSE
25 mfc0 t2,CP0_STATUS
26
27 and t0,t2
28
29 andi t1,t0,STATUSF_IP4 /* int2 hardware line (timer) */
30 bnez t1,ll_gt64120_irq
31 andi t1,t0,STATUSF_IP2 /* int0 hardware line */
32 bnez t1,ll_pci_intA
33 andi t1,t0,STATUSF_IP5 /* int3 hardware line */
34 bnez t1,ll_pci_intD
35 andi t1,t0,STATUSF_IP6 /* int4 hardware line */
36 bnez t1,ll_serial_irq
37 andi t1,t0,STATUSF_IP7 /* compare int */
38 bnez t1,ll_compare_irq
39 nop
40
41 /* wrong alarm or masked ... */
42 j spurious_interrupt
43 nop
44 END(galileo_handle_int)
45
46
47 .align 5
48 .set reorder
49ll_gt64120_irq:
50 li a0,4
51 move a1,sp
52 jal do_IRQ
53 nop
54 j ret_from_irq
55 nop
56
57 .align 5
58 .set reorder
59ll_compare_irq:
60 li a0,7
61 move a1,sp
62 jal do_IRQ
63 nop
64 j ret_from_irq
65 nop
66
67 .align 5
68 .set reorder
69ll_pci_intA:
70 move a0,sp
71 jal pci_intA
72 nop
73 j ret_from_irq
74 nop
75
76#if 0
77 .align 5
78 .set reorder
79ll_pci_intB:
80 move a0,sp
81 jal pci_intB
82 nop
83 j ret_from_irq
84 nop
85
86 .align 5
87 .set reorder
88ll_pci_intC:
89 move a0,sp
90 jal pci_intC
91 nop
92 j ret_from_irq
93 nop
94#endif
95
96 .align 5
97 .set reorder
98ll_pci_intD:
99 move a0,sp
100 jal pci_intD
101 nop
102 j ret_from_irq
103 nop
104
105 .align 5
106 .set reorder
107ll_serial_irq:
108 li a0,6
109 move a1,sp
110 jal do_IRQ
111 nop
112 j ret_from_irq
113 nop
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
new file mode 100644
index 000000000000..3b186159b21a
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -0,0 +1,145 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Code to handle irqs on GT64120A boards
4 * Derived from mips/orion and Cort <cort@fsmlabs.com>
5 *
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: RidgeRun, Inc.
8 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#include <linux/errno.h>
31#include <linux/init.h>
32#include <linux/kernel_stat.h>
33#include <linux/module.h>
34#include <linux/signal.h>
35#include <linux/sched.h>
36#include <linux/types.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/timex.h>
40#include <linux/slab.h>
41#include <linux/random.h>
42#include <linux/bitops.h>
43#include <asm/bootinfo.h>
44#include <asm/io.h>
45#include <asm/mipsregs.h>
46#include <asm/system.h>
47#include <asm/gt64120.h>
48
49asmlinkage inline void pci_intA(struct pt_regs *regs)
50{
51 do_IRQ(GT_INTA, regs);
52}
53
54asmlinkage inline void pci_intD(struct pt_regs *regs)
55{
56 do_IRQ(GT_INTD, regs);
57}
58
59static void disable_ev64120_irq(unsigned int irq_nr)
60{
61 unsigned long flags;
62
63 local_irq_save(flags);
64 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
65 clear_c0_status(9 << 10);
66 } else {
67 clear_c0_status(1 << (irq_nr + 8));
68 }
69 local_irq_restore(flags);
70}
71
72static void enable_ev64120_irq(unsigned int irq_nr)
73{
74 unsigned long flags;
75
76 local_irq_save(flags);
77 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
78 set_c0_status(9 << 10);
79 else
80 set_c0_status(1 << (irq_nr + 8));
81 local_irq_restore(flags);
82}
83
84static unsigned int startup_ev64120_irq(unsigned int irq)
85{
86 enable_ev64120_irq(irq);
87 return 0; /* Never anything pending */
88}
89
90#define shutdown_ev64120_irq disable_ev64120_irq
91#define mask_and_ack_ev64120_irq disable_ev64120_irq
92
93static void end_ev64120_irq(unsigned int irq)
94{
95 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
96 enable_ev64120_irq(irq);
97}
98
99static struct hw_interrupt_type ev64120_irq_type = {
100 .typename = "EV64120",
101 .startup = startup_ev64120_irq,
102 .shutdown = shutdown_ev64120_irq,
103 .enable = enable_ev64120_irq,
104 .disable = disable_ev64120_irq,
105 .ack = mask_and_ack_ev64120_irq,
106 .end = end_ev64120_irq,
107 .set_affinity = NULL
108};
109
110void gt64120_irq_setup(void)
111{
112 extern asmlinkage void galileo_handle_int(void);
113
114 /*
115 * Clear all of the interrupts while we change the able around a bit.
116 */
117 clear_c0_status(ST0_IM);
118
119 /* Sets the exception_handler array. */
120 set_except_vector(0, galileo_handle_int);
121
122 local_irq_disable();
123
124 /*
125 * Enable timer. Other interrupts will be enabled as they are
126 * registered.
127 */
128 set_c0_status(IE_IRQ2);
129}
130
131void __init arch_init_irq(void)
132{
133 int i;
134
135 /* Let's initialize our IRQ descriptors */
136 for (i = 0; i < NR_IRQS; i++) {
137 irq_desc[i].status = 0;
138 irq_desc[i].handler = &no_irq_type;
139 irq_desc[i].action = NULL;
140 irq_desc[i].depth = 0;
141 spin_lock_init(&irq_desc[i].lock);
142 }
143
144 gt64120_irq_setup();
145}
diff --git a/arch/mips/gt64120/ev64120/promcon.c b/arch/mips/gt64120/ev64120/promcon.c
new file mode 100644
index 000000000000..b5937c4ba7db
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/promcon.c
@@ -0,0 +1,53 @@
1/*
2 * Wrap-around code for a console using the
3 * SGI PROM io-routines.
4 *
5 * Copyright (c) 1999 Ulf Carlsson
6 *
7 * Derived from DECstation promcon.c
8 * Copyright (c) 1998 Harald Koerfgen
9 */
10#include <linux/tty.h>
11#include <linux/init.h>
12#include <linux/console.h>
13
14static void prom_console_write(struct console *co, const char *s,
15 unsigned count)
16{
17 extern int CONSOLE_CHANNEL; // The default serial port
18 unsigned i;
19
20 for (i = 0; i < count; i++) {
21 if (*s == 10)
22 serial_putc(CONSOLE_CHANNEL, 13);
23 serial_putc(CONSOLE_CHANNEL, *s++);
24 }
25}
26
27int prom_getchar(void)
28{
29 return 0;
30}
31
32static struct console sercons = {
33 .name = "ttyS",
34 .write = prom_console_write,
35 .flags = CON_PRINTBUFFER,
36 .index = -1,
37};
38
39/*
40 * Register console.
41 */
42
43static int gal_serial_console_init(void)
44{
45 // serial_init();
46 //serial_set(115200);
47
48 register_console(&sercons);
49
50 return 0;
51}
52
53console_initcall(gal_serial_console_init);
diff --git a/arch/mips/gt64120/ev64120/reset.c b/arch/mips/gt64120/ev64120/reset.c
new file mode 100644
index 000000000000..7b9f5e5bf21f
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/reset.c
@@ -0,0 +1,45 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1997 Ralf Baechle
7 */
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <asm/io.h>
11#include <asm/pgtable.h>
12#include <asm/processor.h>
13#include <asm/reboot.h>
14#include <asm/system.h>
15
16void galileo_machine_restart(char *command)
17{
18 *(volatile char *) 0xbc000000 = 0x0f;
19 /*
20 * Ouch, we're still alive ... This time we take the silver bullet ...
21 * ... and find that we leave the hardware in a state in which the
22 * kernel in the flush locks up somewhen during of after the PCI
23 * detection stuff.
24 */
25 set_c0_status(ST0_BEV | ST0_ERL);
26 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
27 flush_cache_all();
28 write_c0_wired(0);
29 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
30}
31
32void galileo_machine_halt(void)
33{
34 printk(KERN_NOTICE "You can safely turn off the power\n");
35 while (1)
36 __asm__(".set\tmips3\n\t"
37 "wait\n\t"
38 ".set\tmips0");
39
40}
41
42void galileo_machine_power_off(void)
43{
44 galileo_machine_halt();
45}
diff --git a/arch/mips/gt64120/ev64120/serialGT.c b/arch/mips/gt64120/ev64120/serialGT.c
new file mode 100644
index 000000000000..16e34a546e54
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/serialGT.c
@@ -0,0 +1,212 @@
1/*
2 * serialGT.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Low Level Serial Port control for use
6 * with the Galileo EVB64120A MIPS eval board and
7 * its on board two channel 16552 Uart.
8 *
9 * Copyright (C) 2000 RidgeRun, Inc.
10 * Author: RidgeRun, Inc.
11 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 */
34
35// Note:
36// Serial CHANNELS - 0 is the bottom connector of evb64120A.
37// (The one that maps to the "B" channel of the
38// board's uart)
39// 1 is the top connector of evb64120A.
40// (The one that maps to the "A" channel of the
41// board's uart)
42int DEBUG_CHANNEL = 0; // See Note Above
43int CONSOLE_CHANNEL = 1; // See Note Above
44
45#define DUART 0xBD000000 /* Base address of Uart. */
46#define CHANNELOFFSET 0x20 /* DUART+CHANNELOFFSET gets you to the ChanA
47 register set of the 16552 Uart device.
48 DUART+0 gets you to the ChanB register set.
49 */
50#define DUART_DELTA 0x4
51#define FIFO_ENABLE 0x07
52#define INT_ENABLE 0x04 /* default interrupt mask */
53
54#define RBR 0x00
55#define THR 0x00
56#define DLL 0x00
57#define IER 0x01
58#define DLM 0x01
59#define IIR 0x02
60#define FCR 0x02
61#define LCR 0x03
62#define MCR 0x04
63#define LSR 0x05
64#define MSR 0x06
65#define SCR 0x07
66
67#define LCR_DLAB 0x80
68#define XTAL 1843200
69#define LSR_THRE 0x20
70#define LSR_BI 0x10
71#define LSR_DR 0x01
72#define MCR_LOOP 0x10
73#define ACCESS_DELAY 0x10000
74
75/******************************
76 Routine:
77 Description:
78 ******************************/
79int inreg(int channel, int reg)
80{
81 int val;
82 val =
83 *((volatile unsigned char *) DUART +
84 (channel * CHANNELOFFSET) + (reg * DUART_DELTA));
85 return val;
86}
87
88/******************************
89 Routine:
90 Description:
91 ******************************/
92void outreg(int channel, int reg, unsigned char val)
93{
94 *((volatile unsigned char *) DUART + (channel * CHANNELOFFSET)
95 + (reg * DUART_DELTA)) = val;
96}
97
98/******************************
99 Routine:
100 Description:
101 Initialize the device driver.
102 ******************************/
103void serial_init(int channel)
104{
105 /*
106 * Configure active port, (CHANNELOFFSET already set.)
107 *
108 * Set 8 bits, 1 stop bit, no parity.
109 *
110 * LCR<7> 0 divisor latch access bit
111 * LCR<6> 0 break control (1=send break)
112 * LCR<5> 0 stick parity (0=space, 1=mark)
113 * LCR<4> 0 parity even (0=odd, 1=even)
114 * LCR<3> 0 parity enable (1=enabled)
115 * LCR<2> 0 # stop bits (0=1, 1=1.5)
116 * LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8)
117 */
118 outreg(channel, LCR, 0x3);
119
120 outreg(channel, FCR, FIFO_ENABLE); /* Enable the FIFO */
121
122 outreg(channel, IER, INT_ENABLE); /* Enable appropriate interrupts */
123}
124
125/******************************
126 Routine:
127 Description:
128 Set the baud rate.
129 ******************************/
130void serial_set(int channel, unsigned long baud)
131{
132 unsigned char sav_lcr;
133
134 /*
135 * Enable access to the divisor latches by setting DLAB in LCR.
136 *
137 */
138 sav_lcr = inreg(channel, LCR);
139
140#if 0
141 /*
142 * Set baud rate
143 */
144 outreg(channel, LCR, LCR_DLAB | sav_lcr);
145 // outreg(DLL,(XTAL/(16*2*(baud))-2));
146 outreg(channel, DLL, XTAL / (16 * baud));
147 // outreg(DLM,(XTAL/(16*2*(baud))-2)>>8);
148 outreg(channel, DLM, (XTAL / (16 * baud)) >> 8);
149#else
150 /*
151 * Note: Set baud rate, hardcoded here for rate of 115200
152 * since became unsure of above "buad rate" algorithm (??).
153 */
154 outreg(channel, LCR, 0x83);
155 outreg(channel, DLM, 0x00); // See note above
156 outreg(channel, DLL, 0x02); // See note above.
157 outreg(channel, LCR, 0x03);
158#endif
159
160 /*
161 * Restore line control register
162 */
163 outreg(channel, LCR, sav_lcr);
164}
165
166
167/******************************
168 Routine:
169 Description:
170 Transmit a character.
171 ******************************/
172void serial_putc(int channel, int c)
173{
174 while ((inreg(channel, LSR) & LSR_THRE) == 0);
175 outreg(channel, THR, c);
176}
177
178/******************************
179 Routine:
180 Description:
181 Read a received character if one is
182 available. Return -1 otherwise.
183 ******************************/
184int serial_getc(int channel)
185{
186 if (inreg(channel, LSR) & LSR_DR) {
187 return inreg(channel, RBR);
188 }
189 return -1;
190}
191
192/******************************
193 Routine:
194 Description:
195 Used by embedded gdb client. (example; gdb-stub.c)
196 ******************************/
197char getDebugChar()
198{
199 int val;
200 while ((val = serial_getc(DEBUG_CHANNEL)) == -1); // loop until we get a character in.
201 return (char) val;
202}
203
204/******************************
205 Routine:
206 Description:
207 Used by embedded gdb target. (example; gdb-stub.c)
208 ******************************/
209void putDebugChar(char c)
210{
211 serial_putc(DEBUG_CHANNEL, (int) c);
212}
diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c
new file mode 100644
index 000000000000..dba0961400cc
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/setup.c
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/types.h>
30#include <linux/mm.h>
31#include <linux/swap.h>
32#include <linux/ioport.h>
33#include <linux/sched.h>
34#include <linux/interrupt.h>
35#include <linux/pci.h>
36#include <linux/timex.h>
37#include <asm/bootinfo.h>
38#include <asm/page.h>
39#include <asm/io.h>
40#include <asm/irq.h>
41#include <asm/pci.h>
42#include <asm/processor.h>
43#include <asm/ptrace.h>
44#include <asm/time.h>
45#include <asm/reboot.h>
46#include <asm/traps.h>
47#include <linux/bootmem.h>
48
49unsigned long gt64120_base = KSEG1ADDR(0x14000000);
50
51/* These functions are used for rebooting or halting the machine*/
52extern void galileo_machine_restart(char *command);
53extern void galileo_machine_halt(void);
54extern void galileo_machine_power_off(void);
55/*
56 *This structure holds pointers to the pci configuration space accesses
57 *and interrupts allocating routine for device over the PCI
58 */
59extern struct pci_ops galileo_pci_ops;
60
61unsigned long __init prom_free_prom_memory(void)
62{
63 return 0;
64}
65
66/*
67 * Initializes basic routines and structures pointers, memory size (as
68 * given by the bios and saves the command line.
69 */
70extern void gt64120_time_init(void);
71
72static void __init ev64120_setup(void)
73{
74 _machine_restart = galileo_machine_restart;
75 _machine_halt = galileo_machine_halt;
76 _machine_power_off = galileo_machine_power_off;
77
78 board_time_init = gt64120_time_init;
79 set_io_port_base(KSEG1);
80}
81
82early_initcall(ev64120_setup);
83
84const char *get_system_type(void)
85{
86 return "Galileo EV64120A";
87}
88
89/*
90 * Kernel arguments passed by the firmware
91 *
92 * $a0 - nothing
93 * $a1 - holds a pointer to the eprom parameters
94 * $a2 - nothing
95 */
96
97void __init prom_init(void)
98{
99 mips_machgroup = MACH_GROUP_GALILEO;
100 mips_machtype = MACH_EV64120A;
101
102 add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
103}
diff --git a/arch/mips/gt64120/momenco_ocelot/Makefile b/arch/mips/gt64120/momenco_ocelot/Makefile
new file mode 100644
index 000000000000..7b59c6567c79
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for Momentum's Ocelot board.
3#
4
5obj-y += int-handler.o irq.o prom.o reset.o setup.o
6
7obj-$(CONFIG_KGDB) += dbg_io.o
8
9EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/gt64120/momenco_ocelot/dbg_io.c b/arch/mips/gt64120/momenco_ocelot/dbg_io.c
new file mode 100644
index 000000000000..8720bccfdea2
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/dbg_io.c
@@ -0,0 +1,126 @@
1#include <linux/config.h>
2
3#ifdef CONFIG_KGDB
4
5#include <asm/serial.h> /* For the serial port location and base baud */
6
7/* --- CONFIG --- */
8
9typedef unsigned char uint8;
10typedef unsigned int uint32;
11
12/* --- END OF CONFIG --- */
13
14#define UART16550_BAUD_2400 2400
15#define UART16550_BAUD_4800 4800
16#define UART16550_BAUD_9600 9600
17#define UART16550_BAUD_19200 19200
18#define UART16550_BAUD_38400 38400
19#define UART16550_BAUD_57600 57600
20#define UART16550_BAUD_115200 115200
21
22#define UART16550_PARITY_NONE 0
23#define UART16550_PARITY_ODD 0x08
24#define UART16550_PARITY_EVEN 0x18
25#define UART16550_PARITY_MARK 0x28
26#define UART16550_PARITY_SPACE 0x38
27
28#define UART16550_DATA_5BIT 0x0
29#define UART16550_DATA_6BIT 0x1
30#define UART16550_DATA_7BIT 0x2
31#define UART16550_DATA_8BIT 0x3
32
33#define UART16550_STOP_1BIT 0x0
34#define UART16550_STOP_2BIT 0x4
35
36/* ----------------------------------------------------- */
37
38/* === CONFIG === */
39
40/* [jsun] we use the second serial port for kdb */
41#define BASE OCELOT_SERIAL1_BASE
42#define MAX_BAUD OCELOT_BASE_BAUD
43
44/* === END OF CONFIG === */
45
46#define REG_OFFSET 4
47
48/* register offset */
49#define OFS_RCV_BUFFER 0
50#define OFS_TRANS_HOLD 0
51#define OFS_SEND_BUFFER 0
52#define OFS_INTR_ENABLE (1*REG_OFFSET)
53#define OFS_INTR_ID (2*REG_OFFSET)
54#define OFS_DATA_FORMAT (3*REG_OFFSET)
55#define OFS_LINE_CONTROL (3*REG_OFFSET)
56#define OFS_MODEM_CONTROL (4*REG_OFFSET)
57#define OFS_RS232_OUTPUT (4*REG_OFFSET)
58#define OFS_LINE_STATUS (5*REG_OFFSET)
59#define OFS_MODEM_STATUS (6*REG_OFFSET)
60#define OFS_RS232_INPUT (6*REG_OFFSET)
61#define OFS_SCRATCH_PAD (7*REG_OFFSET)
62
63#define OFS_DIVISOR_LSB (0*REG_OFFSET)
64#define OFS_DIVISOR_MSB (1*REG_OFFSET)
65
66
67/* memory-mapped read/write of the port */
68#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
69#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
70
71void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
72{
73 /* disable interrupts */
74 UART16550_WRITE(OFS_INTR_ENABLE, 0);
75
76 /* set up buad rate */
77 {
78 uint32 divisor;
79
80 /* set DIAB bit */
81 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
82
83 /* set divisor */
84 divisor = MAX_BAUD / baud;
85 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
86 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
87
88 /* clear DIAB bit */
89 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
90 }
91
92 /* set data format */
93 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
94}
95
96static int remoteDebugInitialized = 0;
97
98uint8 getDebugChar(void)
99{
100 if (!remoteDebugInitialized) {
101 remoteDebugInitialized = 1;
102 debugInit(UART16550_BAUD_38400,
103 UART16550_DATA_8BIT,
104 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
105 }
106
107 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
108 return UART16550_READ(OFS_RCV_BUFFER);
109}
110
111
112int putDebugChar(uint8 byte)
113{
114 if (!remoteDebugInitialized) {
115 remoteDebugInitialized = 1;
116 debugInit(UART16550_BAUD_38400,
117 UART16550_DATA_8BIT,
118 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
119 }
120
121 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
122 UART16550_WRITE(OFS_SEND_BUFFER, byte);
123 return 1;
124}
125
126#endif
diff --git a/arch/mips/gt64120/momenco_ocelot/int-handler.S b/arch/mips/gt64120/momenco_ocelot/int-handler.S
new file mode 100644
index 000000000000..808acef248cc
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/int-handler.S
@@ -0,0 +1,131 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * First-level interrupt dispatcher for ocelot board.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <asm/asm.h>
13#include <asm/mipsregs.h>
14#include <asm/addrspace.h>
15#include <asm/regdef.h>
16#include <asm/stackframe.h>
17
18/*
19 * first level interrupt dispatcher for ocelot board -
20 * We check for the timer first, then check PCI ints A and D.
21 * Then check for serial IRQ and fall through.
22 */
23 .align 5
24 NESTED(ocelot_handle_int, PT_SIZE, sp)
25 SAVE_ALL
26 CLI
27 .set at
28 mfc0 t0, CP0_CAUSE
29 mfc0 t2, CP0_STATUS
30
31 and t0, t2
32
33 andi t1, t0, STATUSF_IP2 /* int0 hardware line */
34 bnez t1, ll_pri_enet_irq
35 andi t1, t0, STATUSF_IP3 /* int1 hardware line */
36 bnez t1, ll_sec_enet_irq
37 andi t1, t0, STATUSF_IP4 /* int2 hardware line */
38 bnez t1, ll_uart1_irq
39 andi t1, t0, STATUSF_IP5 /* int3 hardware line */
40 bnez t1, ll_cpci_irq
41 andi t1, t0, STATUSF_IP6 /* int4 hardware line */
42 bnez t1, ll_galileo_irq
43 andi t1, t0, STATUSF_IP7 /* cpu timer */
44 bnez t1, ll_cputimer_irq
45
46 /* now look at the extended interrupts */
47 mfc0 t0, CP0_CAUSE
48 cfc0 t1, CP0_S1_INTCONTROL
49
50 /* shift the mask 8 bits left to line up the bits */
51 sll t2, t1, 8
52
53 and t0, t2
54 srl t0, t0, 16
55
56 andi t1, t0, STATUSF_IP8 /* int6 hardware line */
57 bnez t1, ll_pmc1_irq
58 andi t1, t0, STATUSF_IP9 /* int7 hardware line */
59 bnez t1, ll_pmc2_irq
60 andi t1, t0, STATUSF_IP10 /* int8 hardware line */
61 bnez t1, ll_cpci_abcd_irq
62 andi t1, t0, STATUSF_IP11 /* int9 hardware line */
63 bnez t1, ll_uart2_irq
64
65 .set reorder
66
67 /* wrong alarm or masked ... */
68 j spurious_interrupt
69 nop
70 END(ocelot_handle_int)
71
72 .align 5
73ll_pri_enet_irq:
74 li a0, 2
75 move a1, sp
76 jal do_IRQ
77 j ret_from_irq
78
79ll_sec_enet_irq:
80 li a0, 3
81 move a1, sp
82 jal do_IRQ
83 j ret_from_irq
84
85ll_uart1_irq:
86 li a0, 4
87 move a1, sp
88 jal do_IRQ
89 j ret_from_irq
90
91ll_cpci_irq:
92 li a0, 5
93 move a1, sp
94 jal do_IRQ
95 j ret_from_irq
96
97ll_galileo_irq:
98 li a0, 6
99 move a1, sp
100 jal do_IRQ
101 j ret_from_irq
102
103ll_cputimer_irq:
104 li a0, 7
105 move a1, sp
106 jal do_IRQ
107 j ret_from_irq
108
109ll_pmc1_irq:
110 li a0, 8
111 move a1, sp
112 jal do_IRQ
113 j ret_from_irq
114
115ll_pmc2_irq:
116 li a0, 9
117 move a1, sp
118 jal do_IRQ
119 j ret_from_irq
120
121ll_cpci_abcd_irq:
122 li a0, 10
123 move a1, sp
124 jal do_IRQ
125 j ret_from_irq
126
127ll_uart2_irq:
128 li a0, 11
129 move a1, sp
130 jal do_IRQ
131 j ret_from_irq
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c
new file mode 100644
index 000000000000..4f108da71b23
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/irq.c
@@ -0,0 +1,67 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <asm/bootinfo.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/irq_cpu.h>
48#include <asm/mipsregs.h>
49#include <asm/system.h>
50
51extern asmlinkage void ocelot_handle_int(void);
52
53void __init arch_init_irq(void)
54{
55 /*
56 * Clear all of the interrupts while we change the able around a bit.
57 * int-handler is not on bootstrap
58 */
59 clear_c0_status(ST0_IM);
60 local_irq_disable();
61
62 /* Sets the first-level interrupt dispatcher. */
63 set_except_vector(0, ocelot_handle_int);
64
65 mips_cpu_irq_init(0);
66 rm7k_cpu_irq_init(8);
67}
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
new file mode 100644
index 000000000000..11f02c402b2a
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
@@ -0,0 +1,30 @@
1/*
2 * Ocelot Board Register Definitions
3 *
4 * (C) 2001 Red Hat, Inc.
5 *
6 * GPL'd
7 */
8#ifndef __MOMENCO_OCELOT_PLD_H__
9#define __MOMENCO_OCELOT_PLD_H__
10
11#define OCELOT_CS0_ADDR (0xe0020000)
12
13#define OCELOT_REG_BOARDREV (0)
14#define OCELOT_REG_PLD1_ID (1)
15#define OCELOT_REG_PLD2_ID (2)
16#define OCELOT_REG_RESET_STATUS (3)
17#define OCELOT_REG_BOARD_STATUS (4)
18#define OCELOT_REG_CPCI_ID (5)
19#define OCELOT_REG_I2C_CTRL (8)
20#define OCELOT_REG_EEPROM_MODE (9)
21#define OCELOT_REG_INTMASK (10)
22#define OCELOT_REG_INTSTATUS (11)
23#define OCELOT_REG_INTSET (12)
24#define OCELOT_REG_INTCLR (13)
25
26#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
27#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
28
29
30#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/gt64120/momenco_ocelot/prom.c b/arch/mips/gt64120/momenco_ocelot/prom.c
new file mode 100644
index 000000000000..8677b6d3ada7
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/prom.c
@@ -0,0 +1,73 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/sched.h>
13#include <linux/bootmem.h>
14
15#include <asm/addrspace.h>
16#include <asm/bootinfo.h>
17#include <asm/pmon.h>
18
19struct callvectors* debug_vectors;
20
21extern unsigned long gt64120_base;
22
23const char *get_system_type(void)
24{
25 return "Momentum Ocelot";
26}
27
28/* [jsun@junsun.net] PMON passes arguments in C main() style */
29void __init prom_init(void)
30{
31 int argc = fw_arg0;
32 char **arg = (char **) fw_arg1;
33 char **env = (char **) fw_arg2;
34 struct callvectors *cv = (struct callvectors *) fw_arg3;
35 uint32_t tmp;
36 int i;
37
38 /* save the PROM vectors for debugging use */
39 debug_vectors = cv;
40
41 /* arg[0] is "g", the rest is boot parameters */
42 arcs_cmdline[0] = '\0';
43 for (i = 1; i < argc; i++) {
44 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
45 >= sizeof(arcs_cmdline))
46 break;
47 strcat(arcs_cmdline, arg[i]);
48 strcat(arcs_cmdline, " ");
49 }
50
51 mips_machgroup = MACH_GROUP_MOMENCO;
52 mips_machtype = MACH_MOMENCO_OCELOT;
53
54 while (*env) {
55 if (strncmp("gtbase", *env, 6) == 0) {
56 gt64120_base = simple_strtol(*env + strlen("gtbase="),
57 NULL, 16);
58 break;
59 }
60 *env++;
61 }
62
63 debug_vectors->printf("Booting Linux kernel...\n");
64
65 /* All the boards have at least 64MiB. If there's more, we
66 detect and register it later */
67 add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
68}
69
70unsigned long __init prom_free_prom_memory(void)
71{
72 return 0;
73}
diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c
new file mode 100644
index 000000000000..3fd499adf4cf
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/reset.c
@@ -0,0 +1,47 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 */
11#include <linux/sched.h>
12#include <linux/mm.h>
13#include <asm/io.h>
14#include <asm/pgtable.h>
15#include <asm/processor.h>
16#include <asm/reboot.h>
17#include <asm/system.h>
18#include <linux/delay.h>
19
20void momenco_ocelot_restart(char *command)
21{
22 void *nvram = ioremap_nocache(0x2c807000, 0x1000);
23
24 if (!nvram) {
25 printk(KERN_NOTICE "ioremap of reset register failed\n");
26 return;
27 }
28 writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
29 assert reset in 1/16 second */
30 mdelay(10+(1000/16));
31 iounmap(nvram);
32 printk(KERN_NOTICE "Watchdog reset failed\n");
33}
34
35void momenco_ocelot_halt(void)
36{
37 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
38 while (1)
39 __asm__(".set\tmips3\n\t"
40 "wait\n\t"
41 ".set\tmips0");
42}
43
44void momenco_ocelot_power_off(void)
45{
46 momenco_ocelot_halt();
47}
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
new file mode 100644
index 000000000000..d610f8c17c81
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -0,0 +1,369 @@
1/*
2 * setup.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Momentum Computer Ocelot (CP7000) - board dependent boot routines
6 *
7 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Copyright (C) 2001 Red Hat, Inc.
10 * Copyright (C) 2002 Momentum Computer
11 *
12 * Author: RidgeRun, Inc.
13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 *
15 * Copyright 2001 MontaVista Software Inc.
16 * Author: jsun@mvista.com or jsun@junsun.net
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 *
38 */
39#include <linux/init.h>
40#include <linux/kernel.h>
41#include <linux/types.h>
42#include <linux/mm.h>
43#include <linux/swap.h>
44#include <linux/ioport.h>
45#include <linux/sched.h>
46#include <linux/interrupt.h>
47#include <linux/pci.h>
48#include <linux/timex.h>
49#include <linux/vmalloc.h>
50#include <asm/time.h>
51#include <asm/bootinfo.h>
52#include <asm/page.h>
53#include <asm/io.h>
54#include <asm/irq.h>
55#include <asm/pci.h>
56#include <asm/processor.h>
57#include <asm/ptrace.h>
58#include <asm/reboot.h>
59#include <asm/traps.h>
60#include <linux/bootmem.h>
61#include <linux/initrd.h>
62#include <asm/gt64120.h>
63#include "ocelot_pld.h"
64
65unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
66
67/* These functions are used for rebooting or halting the machine*/
68extern void momenco_ocelot_restart(char *command);
69extern void momenco_ocelot_halt(void);
70extern void momenco_ocelot_power_off(void);
71
72extern void gt64120_time_init(void);
73extern void momenco_ocelot_irq_setup(void);
74
75static char reset_reason;
76
77#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
78
79static void __init setup_l3cache(unsigned long size);
80
81/* setup code for a handoff from a version 1 PMON 2000 PROM */
82void PMON_v1_setup()
83{
84 /* A wired TLB entry for the GT64120A and the serial port. The
85 GT64120A is going to be hit on every IRQ anyway - there's
86 absolutely no point in letting it be a random TLB entry, as
87 it'll just cause needless churning of the TLB. And we use
88 the other half for the serial port, which is just a PITA
89 otherwise :)
90
91 Device Physical Virtual
92 GT64120 Internal Regs 0x24000000 0xe0000000
93 UARTs (CS2) 0x2d000000 0xe0001000
94 */
95 add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
96
97 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
98 in the CS[012] region. We can't use ioremap() yet. The NVRAM
99 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
100
101 Ocelot PLD (CS0) 0x2c000000 0xe0020000
102 NVRAM 0x2c800000 0xe0030000
103 */
104
105 add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
106
107 /* Relocate the CS3/BootCS region */
108 GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
109
110 /* Relocate CS[012] */
111 GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
112
113 /* Relocate the GT64120A itself... */
114 GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
115 mb();
116 gt64120_base = 0xe0000000;
117
118 /* ...and the PCI0 view of it. */
119 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
120 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
121 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
122 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
123}
124
125/* setup code for a handoff from a version 2 PMON 2000 PROM */
126void PMON_v2_setup()
127{
128 /* A wired TLB entry for the GT64120A and the serial port. The
129 GT64120A is going to be hit on every IRQ anyway - there's
130 absolutely no point in letting it be a random TLB entry, as
131 it'll just cause needless churning of the TLB. And we use
132 the other half for the serial port, which is just a PITA
133 otherwise :)
134
135 Device Physical Virtual
136 GT64120 Internal Regs 0xf4000000 0xe0000000
137 UARTs (CS2) 0xfd000000 0xe0001000
138 */
139 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
140
141 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
142 in the CS[012] region. We can't use ioremap() yet. The NVRAM
143 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
144
145 Ocelot PLD (CS0) 0xfc000000 0xe0020000
146 NVRAM 0xfc800000 0xe0030000
147 */
148 add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
149
150 gt64120_base = 0xe0000000;
151}
152
153static void __init momenco_ocelot_setup(void)
154{
155 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
156 unsigned int tmpword;
157
158 board_time_init = gt64120_time_init;
159
160 _machine_restart = momenco_ocelot_restart;
161 _machine_halt = momenco_ocelot_halt;
162 _machine_power_off = momenco_ocelot_power_off;
163
164 /*
165 * initrd_start = (ulong)ocelot_initrd_start;
166 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
167 * initrd_below_start_ok = 1;
168 */
169
170 /* do handoff reconfiguration */
171 if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
172 PMON_v1_setup();
173 else
174 PMON_v2_setup();
175
176 /* Turn off the Bit-Error LED */
177 OCELOT_PLD_WRITE(0x80, INTCLR);
178
179 /* Relocate all the PCI1 stuff, not that we use it */
180 GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
181 GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
182 GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
183
184 /* Relocate PCI0 I/O and Mem0 */
185 GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
186 GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
187
188 /* Relocate PCI0 Mem1 */
189 GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
190
191 /* For the initial programming, we assume 512MB configuration */
192 /* Relocate the CPU's view of the RAM... */
193 GT_WRITE(GT_SCS10LD_OFS, 0);
194 GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
195 GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
196 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
197
198 GT_WRITE(GT_SCS1LD_OFS, 0xff);
199 GT_WRITE(GT_SCS1HD_OFS, 0x00);
200 GT_WRITE(GT_SCS0LD_OFS, 0);
201 GT_WRITE(GT_SCS0HD_OFS, 0xff);
202 GT_WRITE(GT_SCS3LD_OFS, 0xff);
203 GT_WRITE(GT_SCS3HD_OFS, 0x00);
204 GT_WRITE(GT_SCS2LD_OFS, 0);
205 GT_WRITE(GT_SCS2HD_OFS, 0xff);
206
207 /* ...and the PCI0 view of it. */
208 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
209 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
210 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
211 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
212 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
213 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
214
215 tmpword = OCELOT_PLD_READ(BOARDREV);
216 if (tmpword < 26)
217 printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
218 else
219 printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
220
221 tmpword = OCELOT_PLD_READ(PLD1_ID);
222 printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
223 tmpword = OCELOT_PLD_READ(PLD2_ID);
224 printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
225 tmpword = OCELOT_PLD_READ(RESET_STATUS);
226 printk("Reset reason: 0x%x\n", tmpword);
227 reset_reason = tmpword;
228 OCELOT_PLD_WRITE(0xff, RESET_STATUS);
229
230 tmpword = OCELOT_PLD_READ(BOARD_STATUS);
231 printk("Board Status register: 0x%02x\n", tmpword);
232 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
233 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
234 printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
235 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
236 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
237
238 if (tmpword&12)
239 l3func((1<<(((tmpword&12) >> 2)+20)));
240
241 switch(tmpword &3) {
242 case 3:
243 /* 512MiB */
244 /* Decoders are allready set -- just add the
245 * appropriate region */
246 add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM);
247 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
248 break;
249 case 2:
250 /* 256MiB -- two banks of 128MiB */
251 GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
252 GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
253 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
254
255 GT_WRITE(GT_SCS0HD_OFS, 0x7f);
256 GT_WRITE(GT_SCS2LD_OFS, 0x80);
257 GT_WRITE(GT_SCS2HD_OFS, 0xff);
258
259 /* reconfigure the PCI0 interface view of memory */
260 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
261 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
262 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
263 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
264
265 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
266 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
267 break;
268 case 1:
269 /* 128MiB -- 64MiB per bank */
270 GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
271 GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
272 GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
273
274 GT_WRITE(GT_SCS0HD_OFS, 0x3f);
275 GT_WRITE(GT_SCS2LD_OFS, 0x40);
276 GT_WRITE(GT_SCS2HD_OFS, 0x7f);
277
278 /* reconfigure the PCI0 interface view of memory */
279 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
280 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
281 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
282 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
283
284 /* add the appropriate region */
285 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
286 break;
287 case 0:
288 /* 64MiB */
289 GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
290 GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
291 GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
292
293 GT_WRITE(GT_SCS0HD_OFS, 0x1f);
294 GT_WRITE(GT_SCS2LD_OFS, 0x20);
295 GT_WRITE(GT_SCS2HD_OFS, 0x3f);
296
297 /* reconfigure the PCI0 interface view of memory */
298 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
299 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
300 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
301 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
302
303 break;
304 }
305
306 /* Fix up the DiskOnChip mapping */
307 GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
308}
309
310early_initcall(momenco_ocelot_setup);
311
312extern int rm7k_tcache_enabled;
313/*
314 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
315 */
316#define Page_Invalidate_T 0x16
317static void __init setup_l3cache(unsigned long size)
318{
319 int register i;
320 unsigned long tmp;
321
322 printk("Enabling L3 cache...");
323
324 /* Enable the L3 cache in the GT64120A's CPU Configuration register */
325 tmp = GT_READ(GT_CPU_OFS);
326 GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
327
328 /* Enable the L3 cache in the CPU */
329 set_c0_config(1<<12 /* CONF_TE */);
330
331 /* Clear the cache */
332 write_c0_taglo(0);
333 write_c0_taghi(0);
334
335 for (i=0; i < size; i+= 4096) {
336 __asm__ __volatile__ (
337 ".set noreorder\n\t"
338 ".set mips3\n\t"
339 "cache %1, (%0)\n\t"
340 ".set mips0\n\t"
341 ".set reorder"
342 :
343 : "r" (KSEG0ADDR(i)),
344 "i" (Page_Invalidate_T));
345 }
346
347 /* Let the RM7000 MM code know that the tertiary cache is enabled */
348 rm7k_tcache_enabled = 1;
349
350 printk("Done\n");
351}
352
353
354/* This needs to be one of the first initcalls, because no I/O port access
355 can work before this */
356
357static int io_base_ioremap(void)
358{
359 void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
360
361 if (!io_remap_range) {
362 panic("Could not ioremap I/O port range");
363 }
364 set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
365
366 return 0;
367}
368
369module_init(io_base_ioremap);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 00:18:28 -0500