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-rw-r--r--arch/mips/gt64120/common/Makefile5
-rw-r--r--arch/mips/gt64120/common/time.c101
-rw-r--r--arch/mips/gt64120/momenco_ocelot/Makefile7
-rw-r--r--arch/mips/gt64120/momenco_ocelot/dbg_io.c121
-rw-r--r--arch/mips/gt64120/momenco_ocelot/irq.c95
-rw-r--r--arch/mips/gt64120/momenco_ocelot/ocelot-platform.c46
-rw-r--r--arch/mips/gt64120/momenco_ocelot/ocelot_pld.h30
-rw-r--r--arch/mips/gt64120/momenco_ocelot/prom.c71
-rw-r--r--arch/mips/gt64120/momenco_ocelot/reset.c47
-rw-r--r--arch/mips/gt64120/momenco_ocelot/setup.c365
-rw-r--r--arch/mips/gt64120/wrppmc/Makefile2
11 files changed, 2 insertions, 888 deletions
diff --git a/arch/mips/gt64120/common/Makefile b/arch/mips/gt64120/common/Makefile
deleted file mode 100644
index 1ef676e22ab4..000000000000
--- a/arch/mips/gt64120/common/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for common code of gt64120-based boards.
3#
4
5obj-y += time.o
diff --git a/arch/mips/gt64120/common/time.c b/arch/mips/gt64120/common/time.c
deleted file mode 100644
index c47eeb768192..000000000000
--- a/arch/mips/gt64120/common/time.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Galileo Technology chip interrupt handler
8 */
9#include <linux/interrupt.h>
10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/kernel_stat.h>
13#include <asm/irq_regs.h>
14#include <asm/gt64120.h>
15
16/*
17 * These are interrupt handlers for the GT on-chip interrupts. They all come
18 * in to the MIPS on a single interrupt line, and have to be handled and ack'ed
19 * differently than other MIPS interrupts.
20 */
21
22static irqreturn_t gt64120_irq(int irq, void *dev_id)
23{
24 unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;
25 int handled = 0;
26
27 irq_src = GT_READ(GT_INTRCAUSE_OFS);
28 irq_src_mask = GT_READ(GT_INTRMASK_OFS);
29 int_high_src = GT_READ(GT_HINTRCAUSE_OFS);
30 int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);
31 irq_src = irq_src & irq_src_mask;
32 int_high_src = int_high_src & int_high_src_mask;
33
34 if (irq_src & 0x00000800) { /* Check for timer interrupt */
35 handled = 1;
36 irq_src &= ~0x00000800;
37 do_timer(1);
38#ifndef CONFIG_SMP
39 update_process_times(user_mode(get_irq_regs()));
40#endif
41 }
42
43 GT_WRITE(GT_INTRCAUSE_OFS, 0);
44 GT_WRITE(GT_HINTRCAUSE_OFS, 0);
45
46 return IRQ_HANDLED;
47}
48
49/*
50 * Initializes timer using galileo's built in timer.
51 */
52#ifdef CONFIG_SYSCLK_100
53#define Sys_clock (100 * 1000000) // 100 MHz
54#endif
55#ifdef CONFIG_SYSCLK_83
56#define Sys_clock (83.333 * 1000000) // 83.333 MHz
57#endif
58#ifdef CONFIG_SYSCLK_75
59#define Sys_clock (75 * 1000000) // 75 MHz
60#endif
61
62/*
63 * This will ignore the standard MIPS timer interrupt handler that is passed in
64 * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt
65 * handling.
66 */
67void __init plat_timer_setup(struct irqaction *irq)
68{
69 static struct irqaction timer;
70
71 /* Disable timer first */
72 GT_WRITE(GT_TC_CONTROL_OFS, 0);
73 /* Load timer value for 100 Hz */
74 GT_WRITE(GT_TC3_OFS, Sys_clock / HZ);
75
76 /*
77 * Create the IRQ structure entry for the timer. Since we're too early
78 * in the boot process to use the "request_irq()" call, we'll hard-code
79 * the values to the correct interrupt line.
80 */
81 timer.handler = gt64120_irq;
82 timer.flags = IRQF_SHARED | IRQF_DISABLED;
83 timer.name = "timer";
84 timer.dev_id = NULL;
85 timer.next = NULL;
86 timer.mask = CPU_MASK_NONE;
87 irq_desc[GT_TIMER].action = &timer;
88
89 enable_irq(GT_TIMER);
90
91 /* Enable timer ints */
92 GT_WRITE(GT_TC_CONTROL_OFS, 0xc0);
93 /* clear Cause register first */
94 GT_WRITE(GT_INTRCAUSE_OFS, 0x0);
95 /* Unmask timer int */
96 GT_WRITE(GT_INTRMASK_OFS, 0x800);
97 /* Clear High int register */
98 GT_WRITE(GT_HINTRCAUSE_OFS, 0x0);
99 /* Mask All interrupts at High cause interrupt */
100 GT_WRITE(GT_HINTRMASK_OFS, 0x0);
101}
diff --git a/arch/mips/gt64120/momenco_ocelot/Makefile b/arch/mips/gt64120/momenco_ocelot/Makefile
deleted file mode 100644
index 1df5fe23c642..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for Momentum's Ocelot board.
3#
4
5obj-y += irq.o ocelot-platform.o prom.o reset.o setup.o
6
7obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/gt64120/momenco_ocelot/dbg_io.c b/arch/mips/gt64120/momenco_ocelot/dbg_io.c
deleted file mode 100644
index 32d6fb4ee679..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
1
2#include <asm/serial.h> /* For the serial port location and base baud */
3
4/* --- CONFIG --- */
5
6typedef unsigned char uint8;
7typedef unsigned int uint32;
8
9/* --- END OF CONFIG --- */
10
11#define UART16550_BAUD_2400 2400
12#define UART16550_BAUD_4800 4800
13#define UART16550_BAUD_9600 9600
14#define UART16550_BAUD_19200 19200
15#define UART16550_BAUD_38400 38400
16#define UART16550_BAUD_57600 57600
17#define UART16550_BAUD_115200 115200
18
19#define UART16550_PARITY_NONE 0
20#define UART16550_PARITY_ODD 0x08
21#define UART16550_PARITY_EVEN 0x18
22#define UART16550_PARITY_MARK 0x28
23#define UART16550_PARITY_SPACE 0x38
24
25#define UART16550_DATA_5BIT 0x0
26#define UART16550_DATA_6BIT 0x1
27#define UART16550_DATA_7BIT 0x2
28#define UART16550_DATA_8BIT 0x3
29
30#define UART16550_STOP_1BIT 0x0
31#define UART16550_STOP_2BIT 0x4
32
33/* ----------------------------------------------------- */
34
35/* === CONFIG === */
36
37/* [jsun] we use the second serial port for kdb */
38#define BASE OCELOT_SERIAL1_BASE
39#define MAX_BAUD OCELOT_BASE_BAUD
40
41/* === END OF CONFIG === */
42
43#define REG_OFFSET 4
44
45/* register offset */
46#define OFS_RCV_BUFFER 0
47#define OFS_TRANS_HOLD 0
48#define OFS_SEND_BUFFER 0
49#define OFS_INTR_ENABLE (1*REG_OFFSET)
50#define OFS_INTR_ID (2*REG_OFFSET)
51#define OFS_DATA_FORMAT (3*REG_OFFSET)
52#define OFS_LINE_CONTROL (3*REG_OFFSET)
53#define OFS_MODEM_CONTROL (4*REG_OFFSET)
54#define OFS_RS232_OUTPUT (4*REG_OFFSET)
55#define OFS_LINE_STATUS (5*REG_OFFSET)
56#define OFS_MODEM_STATUS (6*REG_OFFSET)
57#define OFS_RS232_INPUT (6*REG_OFFSET)
58#define OFS_SCRATCH_PAD (7*REG_OFFSET)
59
60#define OFS_DIVISOR_LSB (0*REG_OFFSET)
61#define OFS_DIVISOR_MSB (1*REG_OFFSET)
62
63
64/* memory-mapped read/write of the port */
65#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
66#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
67
68void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
69{
70 /* disable interrupts */
71 UART16550_WRITE(OFS_INTR_ENABLE, 0);
72
73 /* set up baud rate */
74 {
75 uint32 divisor;
76
77 /* set DIAB bit */
78 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
79
80 /* set divisor */
81 divisor = MAX_BAUD / baud;
82 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
83 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
84
85 /* clear DIAB bit */
86 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
87 }
88
89 /* set data format */
90 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
91}
92
93static int remoteDebugInitialized = 0;
94
95uint8 getDebugChar(void)
96{
97 if (!remoteDebugInitialized) {
98 remoteDebugInitialized = 1;
99 debugInit(UART16550_BAUD_38400,
100 UART16550_DATA_8BIT,
101 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
102 }
103
104 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
105 return UART16550_READ(OFS_RCV_BUFFER);
106}
107
108
109int putDebugChar(uint8 byte)
110{
111 if (!remoteDebugInitialized) {
112 remoteDebugInitialized = 1;
113 debugInit(UART16550_BAUD_38400,
114 UART16550_DATA_8BIT,
115 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
116 }
117
118 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
119 UART16550_WRITE(OFS_SEND_BUFFER, byte);
120 return 1;
121}
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c
deleted file mode 100644
index 2585d9dbda33..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/irq.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <asm/bootinfo.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/irq_cpu.h>
48#include <asm/mipsregs.h>
49#include <asm/system.h>
50
51asmlinkage void plat_irq_dispatch(void)
52{
53 unsigned int pending = read_c0_status() & read_c0_cause();
54
55 if (pending & STATUSF_IP2) /* int0 hardware line */
56 do_IRQ(2);
57 else if (pending & STATUSF_IP3) /* int1 hardware line */
58 do_IRQ(3);
59 else if (pending & STATUSF_IP4) /* int2 hardware line */
60 do_IRQ(4);
61 else if (pending & STATUSF_IP5) /* int3 hardware line */
62 do_IRQ(5);
63 else if (pending & STATUSF_IP6) /* int4 hardware line */
64 do_IRQ(6);
65 else if (pending & STATUSF_IP7) /* cpu timer */
66 do_IRQ(7);
67 else {
68 /*
69 * Now look at the extended interrupts
70 */
71 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
72
73 if (pending & STATUSF_IP8) /* int6 hardware line */
74 do_IRQ(8);
75 else if (pending & STATUSF_IP9) /* int7 hardware line */
76 do_IRQ(9);
77 else if (pending & STATUSF_IP10) /* int8 hardware line */
78 do_IRQ(10);
79 else if (pending & STATUSF_IP11) /* int9 hardware line */
80 do_IRQ(11);
81 }
82}
83
84void __init arch_init_irq(void)
85{
86 /*
87 * Clear all of the interrupts while we change the able around a bit.
88 * int-handler is not on bootstrap
89 */
90 clear_c0_status(ST0_IM);
91 local_irq_disable();
92
93 mips_cpu_irq_init();
94 rm7k_cpu_irq_init();
95}
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c b/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c
deleted file mode 100644
index 81d9031a5a2a..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * A NS16552 DUART with a 20MHz crystal.
9 *
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/serial_8250.h>
14
15#define OCELOT_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
16
17static struct plat_serial8250_port uart8250_data[] = {
18 {
19 .mapbase = 0xe0001020,
20 .irq = 4,
21 .uartclk = 20000000,
22 .iotype = UPIO_MEM,
23 .flags = OCELOT_UART_FLAGS,
24 .regshift = 2,
25 },
26 { },
27};
28
29static struct platform_device uart8250_device = {
30 .name = "serial8250",
31 .id = PLAT8250_DEV_PLATFORM,
32 .dev = {
33 .platform_data = uart8250_data,
34 },
35};
36
37static int __init uart8250_init(void)
38{
39 return platform_device_register(&uart8250_device);
40}
41
42module_init(uart8250_init);
43
44MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
45MODULE_LICENSE("GPL");
46MODULE_DESCRIPTION("8250 UART probe driver for the Momenco Ocelot");
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
deleted file mode 100644
index 11f02c402b2a..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Ocelot Board Register Definitions
3 *
4 * (C) 2001 Red Hat, Inc.
5 *
6 * GPL'd
7 */
8#ifndef __MOMENCO_OCELOT_PLD_H__
9#define __MOMENCO_OCELOT_PLD_H__
10
11#define OCELOT_CS0_ADDR (0xe0020000)
12
13#define OCELOT_REG_BOARDREV (0)
14#define OCELOT_REG_PLD1_ID (1)
15#define OCELOT_REG_PLD2_ID (2)
16#define OCELOT_REG_RESET_STATUS (3)
17#define OCELOT_REG_BOARD_STATUS (4)
18#define OCELOT_REG_CPCI_ID (5)
19#define OCELOT_REG_I2C_CTRL (8)
20#define OCELOT_REG_EEPROM_MODE (9)
21#define OCELOT_REG_INTMASK (10)
22#define OCELOT_REG_INTSTATUS (11)
23#define OCELOT_REG_INTSET (12)
24#define OCELOT_REG_INTCLR (13)
25
26#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
27#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
28
29
30#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/gt64120/momenco_ocelot/prom.c b/arch/mips/gt64120/momenco_ocelot/prom.c
deleted file mode 100644
index c71c85276c74..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/prom.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/sched.h>
13#include <linux/bootmem.h>
14
15#include <asm/addrspace.h>
16#include <asm/bootinfo.h>
17#include <asm/pmon.h>
18
19struct callvectors* debug_vectors;
20
21extern unsigned long gt64120_base;
22
23const char *get_system_type(void)
24{
25 return "Momentum Ocelot";
26}
27
28/* [jsun@junsun.net] PMON passes arguments in C main() style */
29void __init prom_init(void)
30{
31 int argc = fw_arg0;
32 char **arg = (char **) fw_arg1;
33 char **env = (char **) fw_arg2;
34 struct callvectors *cv = (struct callvectors *) fw_arg3;
35 int i;
36
37 /* save the PROM vectors for debugging use */
38 debug_vectors = cv;
39
40 /* arg[0] is "g", the rest is boot parameters */
41 arcs_cmdline[0] = '\0';
42 for (i = 1; i < argc; i++) {
43 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
44 >= sizeof(arcs_cmdline))
45 break;
46 strcat(arcs_cmdline, arg[i]);
47 strcat(arcs_cmdline, " ");
48 }
49
50 mips_machgroup = MACH_GROUP_MOMENCO;
51 mips_machtype = MACH_MOMENCO_OCELOT;
52
53 while (*env) {
54 if (strncmp("gtbase", *env, 6) == 0) {
55 gt64120_base = simple_strtol(*env + strlen("gtbase="),
56 NULL, 16);
57 break;
58 }
59 *env++;
60 }
61
62 debug_vectors->printf("Booting Linux kernel...\n");
63
64 /* All the boards have at least 64MiB. If there's more, we
65 detect and register it later */
66 add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
67}
68
69void __init prom_free_prom_memory(void)
70{
71}
diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c
deleted file mode 100644
index 3fd499adf4cf..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/reset.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 */
11#include <linux/sched.h>
12#include <linux/mm.h>
13#include <asm/io.h>
14#include <asm/pgtable.h>
15#include <asm/processor.h>
16#include <asm/reboot.h>
17#include <asm/system.h>
18#include <linux/delay.h>
19
20void momenco_ocelot_restart(char *command)
21{
22 void *nvram = ioremap_nocache(0x2c807000, 0x1000);
23
24 if (!nvram) {
25 printk(KERN_NOTICE "ioremap of reset register failed\n");
26 return;
27 }
28 writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
29 assert reset in 1/16 second */
30 mdelay(10+(1000/16));
31 iounmap(nvram);
32 printk(KERN_NOTICE "Watchdog reset failed\n");
33}
34
35void momenco_ocelot_halt(void)
36{
37 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
38 while (1)
39 __asm__(".set\tmips3\n\t"
40 "wait\n\t"
41 ".set\tmips0");
42}
43
44void momenco_ocelot_power_off(void)
45{
46 momenco_ocelot_halt();
47}
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
deleted file mode 100644
index 98b6fb38096d..000000000000
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ /dev/null
@@ -1,365 +0,0 @@
1/*
2 * setup.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Momentum Computer Ocelot (CP7000) - board dependent boot routines
6 *
7 * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Copyright (C) 2001 Red Hat, Inc.
10 * Copyright (C) 2002 Momentum Computer
11 *
12 * Author: RidgeRun, Inc.
13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 *
15 * Copyright 2001 MontaVista Software Inc.
16 * Author: jsun@mvista.com or jsun@junsun.net
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 *
38 */
39#include <linux/init.h>
40#include <linux/kernel.h>
41#include <linux/types.h>
42#include <linux/mm.h>
43#include <linux/swap.h>
44#include <linux/ioport.h>
45#include <linux/sched.h>
46#include <linux/interrupt.h>
47#include <linux/pci.h>
48#include <linux/timex.h>
49#include <linux/vmalloc.h>
50#include <linux/pm.h>
51
52#include <asm/time.h>
53#include <asm/bootinfo.h>
54#include <asm/page.h>
55#include <asm/io.h>
56#include <asm/irq.h>
57#include <asm/pci.h>
58#include <asm/processor.h>
59#include <asm/reboot.h>
60#include <asm/traps.h>
61#include <linux/bootmem.h>
62#include <linux/initrd.h>
63#include <asm/gt64120.h>
64#include "ocelot_pld.h"
65
66unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
67
68/* These functions are used for rebooting or halting the machine*/
69extern void momenco_ocelot_restart(char *command);
70extern void momenco_ocelot_halt(void);
71extern void momenco_ocelot_power_off(void);
72
73extern void momenco_ocelot_irq_setup(void);
74
75static char reset_reason;
76
77#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
78
79static void __init setup_l3cache(unsigned long size);
80
81/* setup code for a handoff from a version 1 PMON 2000 PROM */
82static void PMON_v1_setup(void)
83{
84 /* A wired TLB entry for the GT64120A and the serial port. The
85 GT64120A is going to be hit on every IRQ anyway - there's
86 absolutely no point in letting it be a random TLB entry, as
87 it'll just cause needless churning of the TLB. And we use
88 the other half for the serial port, which is just a PITA
89 otherwise :)
90
91 Device Physical Virtual
92 GT64120 Internal Regs 0x24000000 0xe0000000
93 UARTs (CS2) 0x2d000000 0xe0001000
94 */
95 add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
96
97 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
98 in the CS[012] region. We can't use ioremap() yet. The NVRAM
99 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
100
101 Ocelot PLD (CS0) 0x2c000000 0xe0020000
102 NVRAM 0x2c800000 0xe0030000
103 */
104
105 add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
106
107 /* Relocate the CS3/BootCS region */
108 GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
109
110 /* Relocate CS[012] */
111 GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
112
113 /* Relocate the GT64120A itself... */
114 GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
115 mb();
116 gt64120_base = 0xe0000000;
117
118 /* ...and the PCI0 view of it. */
119 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
120 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
121 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
122 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
123}
124
125/* setup code for a handoff from a version 2 PMON 2000 PROM */
126void PMON_v2_setup()
127{
128 /* A wired TLB entry for the GT64120A and the serial port. The
129 GT64120A is going to be hit on every IRQ anyway - there's
130 absolutely no point in letting it be a random TLB entry, as
131 it'll just cause needless churning of the TLB. And we use
132 the other half for the serial port, which is just a PITA
133 otherwise :)
134
135 Device Physical Virtual
136 GT64120 Internal Regs 0xf4000000 0xe0000000
137 UARTs (CS2) 0xfd000000 0xe0001000
138 */
139 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
140
141 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
142 in the CS[012] region. We can't use ioremap() yet. The NVRAM
143 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
144
145 Ocelot PLD (CS0) 0xfc000000 0xe0020000
146 NVRAM 0xfc800000 0xe0030000
147 */
148 add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
149
150 gt64120_base = 0xe0000000;
151}
152
153void __init plat_mem_setup(void)
154{
155 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
156 unsigned int tmpword;
157
158 _machine_restart = momenco_ocelot_restart;
159 _machine_halt = momenco_ocelot_halt;
160 pm_power_off = momenco_ocelot_power_off;
161
162 /*
163 * initrd_start = (unsigned long)ocelot_initrd_start;
164 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
165 * initrd_below_start_ok = 1;
166 */
167
168 /* do handoff reconfiguration */
169 if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
170 PMON_v1_setup();
171 else
172 PMON_v2_setup();
173
174 /* Turn off the Bit-Error LED */
175 OCELOT_PLD_WRITE(0x80, INTCLR);
176
177 /* Relocate all the PCI1 stuff, not that we use it */
178 GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
179 GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
180 GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
181
182 /* Relocate PCI0 I/O and Mem0 */
183 GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
184 GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
185
186 /* Relocate PCI0 Mem1 */
187 GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
188
189 /* For the initial programming, we assume 512MB configuration */
190 /* Relocate the CPU's view of the RAM... */
191 GT_WRITE(GT_SCS10LD_OFS, 0);
192 GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
193 GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
194 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
195
196 GT_WRITE(GT_SCS1LD_OFS, 0xff);
197 GT_WRITE(GT_SCS1HD_OFS, 0x00);
198 GT_WRITE(GT_SCS0LD_OFS, 0);
199 GT_WRITE(GT_SCS0HD_OFS, 0xff);
200 GT_WRITE(GT_SCS3LD_OFS, 0xff);
201 GT_WRITE(GT_SCS3HD_OFS, 0x00);
202 GT_WRITE(GT_SCS2LD_OFS, 0);
203 GT_WRITE(GT_SCS2HD_OFS, 0xff);
204
205 /* ...and the PCI0 view of it. */
206 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
207 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
208 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
209 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
210 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
211 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
212
213 tmpword = OCELOT_PLD_READ(BOARDREV);
214 if (tmpword < 26)
215 printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
216 else
217 printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
218
219 tmpword = OCELOT_PLD_READ(PLD1_ID);
220 printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
221 tmpword = OCELOT_PLD_READ(PLD2_ID);
222 printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
223 tmpword = OCELOT_PLD_READ(RESET_STATUS);
224 printk("Reset reason: 0x%x\n", tmpword);
225 reset_reason = tmpword;
226 OCELOT_PLD_WRITE(0xff, RESET_STATUS);
227
228 tmpword = OCELOT_PLD_READ(BOARD_STATUS);
229 printk("Board Status register: 0x%02x\n", tmpword);
230 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
231 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
232 printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
233 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
234 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
235
236 if (tmpword&12)
237 l3func((1<<(((tmpword&12) >> 2)+20)));
238
239 switch(tmpword &3) {
240 case 3:
241 /* 512MiB */
242 /* Decoders are allready set -- just add the
243 * appropriate region */
244 add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM);
245 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
246 break;
247 case 2:
248 /* 256MiB -- two banks of 128MiB */
249 GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
250 GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
251 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
252
253 GT_WRITE(GT_SCS0HD_OFS, 0x7f);
254 GT_WRITE(GT_SCS2LD_OFS, 0x80);
255 GT_WRITE(GT_SCS2HD_OFS, 0xff);
256
257 /* reconfigure the PCI0 interface view of memory */
258 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
259 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
260 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
261 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
262
263 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
264 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
265 break;
266 case 1:
267 /* 128MiB -- 64MiB per bank */
268 GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
269 GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
270 GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
271
272 GT_WRITE(GT_SCS0HD_OFS, 0x3f);
273 GT_WRITE(GT_SCS2LD_OFS, 0x40);
274 GT_WRITE(GT_SCS2HD_OFS, 0x7f);
275
276 /* reconfigure the PCI0 interface view of memory */
277 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
278 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
279 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
280 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
281
282 /* add the appropriate region */
283 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
284 break;
285 case 0:
286 /* 64MiB */
287 GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
288 GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
289 GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
290
291 GT_WRITE(GT_SCS0HD_OFS, 0x1f);
292 GT_WRITE(GT_SCS2LD_OFS, 0x20);
293 GT_WRITE(GT_SCS2HD_OFS, 0x3f);
294
295 /* reconfigure the PCI0 interface view of memory */
296 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
297 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
298 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
299 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
300
301 break;
302 }
303
304 /* Fix up the DiskOnChip mapping */
305 GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
306}
307
308extern int rm7k_tcache_enabled;
309/*
310 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
311 */
312#define Page_Invalidate_T 0x16
313static void __init setup_l3cache(unsigned long size)
314{
315 int register i;
316 unsigned long tmp;
317
318 printk("Enabling L3 cache...");
319
320 /* Enable the L3 cache in the GT64120A's CPU Configuration register */
321 tmp = GT_READ(GT_CPU_OFS);
322 GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
323
324 /* Enable the L3 cache in the CPU */
325 set_c0_config(1<<12 /* CONF_TE */);
326
327 /* Clear the cache */
328 write_c0_taglo(0);
329 write_c0_taghi(0);
330
331 for (i=0; i < size; i+= 4096) {
332 __asm__ __volatile__ (
333 ".set noreorder\n\t"
334 ".set mips3\n\t"
335 "cache %1, (%0)\n\t"
336 ".set mips0\n\t"
337 ".set reorder"
338 :
339 : "r" (KSEG0ADDR(i)),
340 "i" (Page_Invalidate_T));
341 }
342
343 /* Let the RM7000 MM code know that the tertiary cache is enabled */
344 rm7k_tcache_enabled = 1;
345
346 printk("Done\n");
347}
348
349
350/* This needs to be one of the first initcalls, because no I/O port access
351 can work before this */
352
353static int io_base_ioremap(void)
354{
355 void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
356
357 if (!io_remap_range) {
358 panic("Could not ioremap I/O port range");
359 }
360 set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
361
362 return 0;
363}
364
365module_init(io_base_ioremap);
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile
index e4250435ad89..bef15c90ae15 100644
--- a/arch/mips/gt64120/wrppmc/Makefile
+++ b/arch/mips/gt64120/wrppmc/Makefile
@@ -10,3 +10,5 @@
10# 10#
11 11
12obj-y += irq.o reset.o setup.o time.o pci.o 12obj-y += irq.o reset.o setup.o time.o pci.o
13
14EXTRA_CFLAGS += -Werror
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 05:17:31 -0500