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-rw-r--r--arch/mips/gt64120/wrppmc/setup.c34
1 files changed, 0 insertions, 34 deletions
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c
index f2ccf101e6d9..51f6b7862460 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/gt64120/wrppmc/setup.c
@@ -11,10 +11,6 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/string.h> 12#include <linux/string.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/tty.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/serial_8250.h>
18#include <linux/pm.h> 14#include <linux/pm.h>
19 15
20#include <asm/io.h> 16#include <asm/io.h>
@@ -98,32 +94,6 @@ void __init prom_free_prom_memory(void)
98{ 94{
99} 95}
100 96
101#ifdef CONFIG_SERIAL_8250
102static void wrppmc_setup_serial(void)
103{
104 struct uart_port up;
105
106 memset(&up, 0x00, sizeof(struct uart_port));
107
108 /*
109 * A note about mapbase/membase
110 * -) mapbase is the physical address of the IO port.
111 * -) membase is an 'ioremapped' cookie.
112 */
113 up.line = 0;
114 up.type = PORT_16550;
115 up.iotype = UPIO_MEM;
116 up.mapbase = WRPPMC_UART16550_BASE;
117 up.membase = ioremap(up.mapbase, 8);
118 up.irq = WRPPMC_UART16550_IRQ;
119 up.uartclk = WRPPMC_UART16550_CLOCK;
120 up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */;
121 up.regshift = 0;
122
123 early_serial_setup(&up);
124}
125#endif
126
127void __init plat_mem_setup(void) 97void __init plat_mem_setup(void)
128{ 98{
129 extern void wrppmc_machine_restart(char *command); 99 extern void wrppmc_machine_restart(char *command);
@@ -138,10 +108,6 @@ void __init plat_mem_setup(void)
138 * physical address ( < KSEG0) can work via KSEG1 108 * physical address ( < KSEG0) can work via KSEG1
139 */ 109 */
140 set_io_port_base(KSEG1); 110 set_io_port_base(KSEG1);
141
142#ifdef CONFIG_SERIAL_8250
143 wrppmc_setup_serial();
144#endif
145} 111}
146 112
147const char *get_system_type(void) 113const char *get_system_type(void)