diff options
Diffstat (limited to 'arch/mips/gt64120/ev64120/irq.c')
| -rw-r--r-- | arch/mips/gt64120/ev64120/irq.c | 116 |
1 files changed, 0 insertions, 116 deletions
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c deleted file mode 100644 index 64e4c80b6139..000000000000 --- a/arch/mips/gt64120/ev64120/irq.c +++ /dev/null | |||
| @@ -1,116 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * BRIEF MODULE DESCRIPTION | ||
| 3 | * Code to handle irqs on GT64120A boards | ||
| 4 | * Derived from mips/orion and Cort <cort@fsmlabs.com> | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000 RidgeRun, Inc. | ||
| 7 | * Author: RidgeRun, Inc. | ||
| 8 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License along | ||
| 27 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 29 | */ | ||
| 30 | #include <linux/errno.h> | ||
| 31 | #include <linux/init.h> | ||
| 32 | #include <linux/kernel_stat.h> | ||
| 33 | #include <linux/module.h> | ||
| 34 | #include <linux/signal.h> | ||
| 35 | #include <linux/sched.h> | ||
| 36 | #include <linux/types.h> | ||
| 37 | #include <linux/interrupt.h> | ||
| 38 | #include <linux/ioport.h> | ||
| 39 | #include <linux/timex.h> | ||
| 40 | #include <linux/slab.h> | ||
| 41 | #include <linux/random.h> | ||
| 42 | #include <linux/bitops.h> | ||
| 43 | #include <asm/bootinfo.h> | ||
| 44 | #include <asm/io.h> | ||
| 45 | #include <asm/mipsregs.h> | ||
| 46 | #include <asm/system.h> | ||
| 47 | #include <asm/gt64120.h> | ||
| 48 | |||
| 49 | asmlinkage void plat_irq_dispatch(void) | ||
| 50 | { | ||
| 51 | unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; | ||
| 52 | |||
| 53 | if (pending & STATUSF_IP4) /* int2 hardware line (timer) */ | ||
| 54 | do_IRQ(4); | ||
| 55 | else if (pending & STATUSF_IP2) /* int0 hardware line */ | ||
| 56 | do_IRQ(GT_INTA); | ||
| 57 | else if (pending & STATUSF_IP5) /* int3 hardware line */ | ||
| 58 | do_IRQ(GT_INTD); | ||
| 59 | else if (pending & STATUSF_IP6) /* int4 hardware line */ | ||
| 60 | do_IRQ(6); | ||
| 61 | else if (pending & STATUSF_IP7) /* compare int */ | ||
| 62 | do_IRQ(7); | ||
| 63 | else | ||
| 64 | spurious_interrupt(); | ||
| 65 | } | ||
| 66 | |||
| 67 | static void disable_ev64120_irq(unsigned int irq_nr) | ||
| 68 | { | ||
| 69 | if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 | ||
| 70 | clear_c0_status(9 << 10); | ||
| 71 | } else { | ||
| 72 | clear_c0_status(1 << (irq_nr + 8)); | ||
| 73 | } | ||
| 74 | } | ||
| 75 | |||
| 76 | static void enable_ev64120_irq(unsigned int irq_nr) | ||
| 77 | { | ||
| 78 | if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2 | ||
| 79 | set_c0_status(9 << 10); | ||
| 80 | else | ||
| 81 | set_c0_status(1 << (irq_nr + 8)); | ||
| 82 | } | ||
| 83 | |||
| 84 | static void end_ev64120_irq(unsigned int irq) | ||
| 85 | { | ||
| 86 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
| 87 | enable_ev64120_irq(irq); | ||
| 88 | } | ||
| 89 | |||
| 90 | static struct irq_chip ev64120_irq_type = { | ||
| 91 | .name = "EV64120", | ||
| 92 | .ack = disable_ev64120_irq, | ||
| 93 | .mask = disable_ev64120_irq, | ||
| 94 | .mask_ack = disable_ev64120_irq, | ||
| 95 | .unmask = enable_ev64120_irq, | ||
| 96 | .end = end_ev64120_irq, | ||
| 97 | }; | ||
| 98 | |||
| 99 | void gt64120_irq_setup(void) | ||
| 100 | { | ||
| 101 | /* | ||
| 102 | * Clear all of the interrupts while we change the able around a bit. | ||
| 103 | */ | ||
| 104 | clear_c0_status(ST0_IM); | ||
| 105 | |||
| 106 | /* | ||
| 107 | * Enable timer. Other interrupts will be enabled as they are | ||
| 108 | * registered. | ||
| 109 | */ | ||
| 110 | set_c0_status(IE_IRQ2); | ||
| 111 | } | ||
| 112 | |||
| 113 | void __init arch_init_irq(void) | ||
| 114 | { | ||
| 115 | gt64120_irq_setup(); | ||
| 116 | } | ||