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-rw-r--r--arch/mips/galileo-boards/ev96100/setup.c159
1 files changed, 0 insertions, 159 deletions
diff --git a/arch/mips/galileo-boards/ev96100/setup.c b/arch/mips/galileo-boards/ev96100/setup.c
deleted file mode 100644
index 639ad5562c63..000000000000
--- a/arch/mips/galileo-boards/ev96100/setup.c
+++ /dev/null
@@ -1,159 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Galileo EV96100 setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This file was derived from Carsten Langgaard's
10 * arch/mips/mips-boards/atlas/atlas_setup.c.
11 *
12 * Carsten Langgaard, carstenl@mips.com
13 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/init.h>
36#include <linux/sched.h>
37#include <linux/ioport.h>
38#include <linux/string.h>
39#include <linux/ctype.h>
40#include <linux/pci.h>
41
42#include <asm/cpu.h>
43#include <asm/bootinfo.h>
44#include <asm/mipsregs.h>
45#include <asm/irq.h>
46#include <asm/delay.h>
47#include <asm/gt64120.h>
48#include <asm/galileo-boards/ev96100int.h>
49
50
51extern char *__init prom_getcmdline(void);
52
53extern void mips_reboot_setup(void);
54
55unsigned char mac_0_1[12];
56
57void __init plat_mem_setup(void)
58{
59 unsigned int config = read_c0_config();
60 unsigned int status = read_c0_status();
61 unsigned int info = read_c0_info();
62 u32 tmp;
63
64 char *argptr;
65
66 clear_c0_status(ST0_FR);
67
68 if (config & 0x8)
69 printk("Secondary cache is enabled\n");
70 else
71 printk("Secondary cache is disabled\n");
72
73 if (status & (1 << 27))
74 printk("User-mode cache ops enabled\n");
75 else
76 printk("User-mode cache ops disabled\n");
77
78 printk("CP0 info reg: %x\n", (unsigned) info);
79 if (info & (1 << 28))
80 printk("burst mode Scache RAMS\n");
81 else
82 printk("pipelined Scache RAMS\n");
83
84 if (info & 0x1)
85 printk("Atomic Enable is set\n");
86
87 argptr = prom_getcmdline();
88#ifdef CONFIG_SERIAL_CONSOLE
89 if (strstr(argptr, "console=") == NULL) {
90 argptr = prom_getcmdline();
91 strcat(argptr, " console=ttyS0,115200");
92 }
93#endif
94
95 mips_reboot_setup();
96
97 set_io_port_base(KSEG1);
98 ioport_resource.start = GT_PCI_IO_BASE;
99 ioport_resource.end = GT_PCI_IO_BASE + 0x01ffffff;
100
101#ifdef CONFIG_BLK_DEV_INITRD
102 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
103#endif
104
105
106 /*
107 * Setup GT controller master bit so we can do config cycles
108 */
109
110 /* Clear cause register bits */
111 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
112 GT_INTRCAUSE_TARABORT0_BIT));
113 /* Setup address */
114 GT_WRITE(GT_PCI0_CFGADDR_OFS,
115 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
116 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
117 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
118 GT_PCI0_CFGADDR_CONFIGEN_BIT);
119
120 udelay(2);
121 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
122
123 tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
124 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
125 GT_WRITE(GT_PCI0_CFGADDR_OFS,
126 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
127 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
128 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
129 GT_PCI0_CFGADDR_CONFIGEN_BIT);
130 udelay(2);
131 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
132
133 /* Setup address */
134 GT_WRITE(GT_PCI0_CFGADDR_OFS,
135 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
136 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
137 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
138 GT_PCI0_CFGADDR_CONFIGEN_BIT);
139
140 udelay(2);
141 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
142}
143
144unsigned short get_gt_devid(void)
145{
146 u32 gt_devid;
147
148 /* Figure out if this is a gt96100 or gt96100A */
149 GT_WRITE(GT_PCI0_CFGADDR_OFS,
150 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
151 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
152 ((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
153 GT_PCI0_CFGADDR_CONFIGEN_BIT);
154
155 udelay(4);
156 gt_devid = GT_READ(GT_PCI0_CFGDATA_OFS);
157
158 return gt_devid >> 16;
159}
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