diff options
Diffstat (limited to 'arch/mips/dec')
-rw-r--r-- | arch/mips/dec/ecc-berr.c | 6 | ||||
-rw-r--r-- | arch/mips/dec/ioasic-irq.c | 72 | ||||
-rw-r--r-- | arch/mips/dec/kn02-irq.c | 53 |
3 files changed, 20 insertions, 111 deletions
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c index 3e374d05978f..c8430c07355e 100644 --- a/arch/mips/dec/ecc-berr.c +++ b/arch/mips/dec/ecc-berr.c | |||
@@ -18,7 +18,6 @@ | |||
18 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
20 | #include <linux/sched.h> | 20 | #include <linux/sched.h> |
21 | #include <linux/spinlock.h> | ||
22 | #include <linux/types.h> | 21 | #include <linux/types.h> |
23 | 22 | ||
24 | #include <asm/addrspace.h> | 23 | #include <asm/addrspace.h> |
@@ -231,13 +230,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id) | |||
231 | static inline void dec_kn02_be_init(void) | 230 | static inline void dec_kn02_be_init(void) |
232 | { | 231 | { |
233 | volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); | 232 | volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); |
234 | unsigned long flags; | ||
235 | 233 | ||
236 | kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); | 234 | kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); |
237 | kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); | 235 | kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); |
238 | 236 | ||
239 | spin_lock_irqsave(&kn02_lock, flags); | ||
240 | |||
241 | /* Preset write-only bits of the Control Register cache. */ | 237 | /* Preset write-only bits of the Control Register cache. */ |
242 | cached_kn02_csr = *csr | KN02_CSR_LEDS; | 238 | cached_kn02_csr = *csr | KN02_CSR_LEDS; |
243 | 239 | ||
@@ -247,8 +243,6 @@ static inline void dec_kn02_be_init(void) | |||
247 | cached_kn02_csr |= KN02_CSR_CORRECT; | 243 | cached_kn02_csr |= KN02_CSR_CORRECT; |
248 | *csr = cached_kn02_csr; | 244 | *csr = cached_kn02_csr; |
249 | iob(); | 245 | iob(); |
250 | |||
251 | spin_unlock_irqrestore(&kn02_lock, flags); | ||
252 | } | 246 | } |
253 | 247 | ||
254 | static inline void dec_kn03_be_init(void) | 248 | static inline void dec_kn03_be_init(void) |
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index 41cd2a96148b..d0af08bdbb4e 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c | |||
@@ -13,7 +13,6 @@ | |||
13 | 13 | ||
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
16 | #include <linux/spinlock.h> | ||
17 | #include <linux/types.h> | 16 | #include <linux/types.h> |
18 | 17 | ||
19 | #include <asm/dec/ioasic.h> | 18 | #include <asm/dec/ioasic.h> |
@@ -21,8 +20,6 @@ | |||
21 | #include <asm/dec/ioasic_ints.h> | 20 | #include <asm/dec/ioasic_ints.h> |
22 | 21 | ||
23 | 22 | ||
24 | static DEFINE_SPINLOCK(ioasic_lock); | ||
25 | |||
26 | static int ioasic_irq_base; | 23 | static int ioasic_irq_base; |
27 | 24 | ||
28 | 25 | ||
@@ -52,65 +49,31 @@ static inline void clear_ioasic_irq(unsigned int irq) | |||
52 | ioasic_write(IO_REG_SIR, sir); | 49 | ioasic_write(IO_REG_SIR, sir); |
53 | } | 50 | } |
54 | 51 | ||
55 | static inline void enable_ioasic_irq(unsigned int irq) | ||
56 | { | ||
57 | unsigned long flags; | ||
58 | |||
59 | spin_lock_irqsave(&ioasic_lock, flags); | ||
60 | unmask_ioasic_irq(irq); | ||
61 | spin_unlock_irqrestore(&ioasic_lock, flags); | ||
62 | } | ||
63 | |||
64 | static inline void disable_ioasic_irq(unsigned int irq) | ||
65 | { | ||
66 | unsigned long flags; | ||
67 | |||
68 | spin_lock_irqsave(&ioasic_lock, flags); | ||
69 | mask_ioasic_irq(irq); | ||
70 | spin_unlock_irqrestore(&ioasic_lock, flags); | ||
71 | } | ||
72 | |||
73 | |||
74 | static inline unsigned int startup_ioasic_irq(unsigned int irq) | ||
75 | { | ||
76 | enable_ioasic_irq(irq); | ||
77 | return 0; | ||
78 | } | ||
79 | |||
80 | #define shutdown_ioasic_irq disable_ioasic_irq | ||
81 | |||
82 | static inline void ack_ioasic_irq(unsigned int irq) | 52 | static inline void ack_ioasic_irq(unsigned int irq) |
83 | { | 53 | { |
84 | spin_lock(&ioasic_lock); | ||
85 | mask_ioasic_irq(irq); | 54 | mask_ioasic_irq(irq); |
86 | spin_unlock(&ioasic_lock); | ||
87 | fast_iob(); | 55 | fast_iob(); |
88 | } | 56 | } |
89 | 57 | ||
90 | static inline void end_ioasic_irq(unsigned int irq) | 58 | static inline void end_ioasic_irq(unsigned int irq) |
91 | { | 59 | { |
92 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | 60 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
93 | enable_ioasic_irq(irq); | 61 | unmask_ioasic_irq(irq); |
94 | } | 62 | } |
95 | 63 | ||
96 | static struct irq_chip ioasic_irq_type = { | 64 | static struct irq_chip ioasic_irq_type = { |
97 | .typename = "IO-ASIC", | 65 | .typename = "IO-ASIC", |
98 | .startup = startup_ioasic_irq, | ||
99 | .shutdown = shutdown_ioasic_irq, | ||
100 | .enable = enable_ioasic_irq, | ||
101 | .disable = disable_ioasic_irq, | ||
102 | .ack = ack_ioasic_irq, | 66 | .ack = ack_ioasic_irq, |
67 | .mask = mask_ioasic_irq, | ||
68 | .mask_ack = ack_ioasic_irq, | ||
69 | .unmask = unmask_ioasic_irq, | ||
103 | .end = end_ioasic_irq, | 70 | .end = end_ioasic_irq, |
104 | }; | 71 | }; |
105 | 72 | ||
106 | 73 | ||
107 | #define startup_ioasic_dma_irq startup_ioasic_irq | 74 | #define unmask_ioasic_dma_irq unmask_ioasic_irq |
108 | |||
109 | #define shutdown_ioasic_dma_irq shutdown_ioasic_irq | ||
110 | |||
111 | #define enable_ioasic_dma_irq enable_ioasic_irq | ||
112 | 75 | ||
113 | #define disable_ioasic_dma_irq disable_ioasic_irq | 76 | #define mask_ioasic_dma_irq mask_ioasic_irq |
114 | 77 | ||
115 | #define ack_ioasic_dma_irq ack_ioasic_irq | 78 | #define ack_ioasic_dma_irq ack_ioasic_irq |
116 | 79 | ||
@@ -123,11 +86,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq) | |||
123 | 86 | ||
124 | static struct irq_chip ioasic_dma_irq_type = { | 87 | static struct irq_chip ioasic_dma_irq_type = { |
125 | .typename = "IO-ASIC-DMA", | 88 | .typename = "IO-ASIC-DMA", |
126 | .startup = startup_ioasic_dma_irq, | ||
127 | .shutdown = shutdown_ioasic_dma_irq, | ||
128 | .enable = enable_ioasic_dma_irq, | ||
129 | .disable = disable_ioasic_dma_irq, | ||
130 | .ack = ack_ioasic_dma_irq, | 89 | .ack = ack_ioasic_dma_irq, |
90 | .mask = mask_ioasic_dma_irq, | ||
91 | .mask_ack = ack_ioasic_dma_irq, | ||
92 | .unmask = unmask_ioasic_dma_irq, | ||
131 | .end = end_ioasic_dma_irq, | 93 | .end = end_ioasic_dma_irq, |
132 | }; | 94 | }; |
133 | 95 | ||
@@ -140,18 +102,10 @@ void __init init_ioasic_irqs(int base) | |||
140 | ioasic_write(IO_REG_SIMR, 0); | 102 | ioasic_write(IO_REG_SIMR, 0); |
141 | fast_iob(); | 103 | fast_iob(); |
142 | 104 | ||
143 | for (i = base; i < base + IO_INR_DMA; i++) { | 105 | for (i = base; i < base + IO_INR_DMA; i++) |
144 | irq_desc[i].status = IRQ_DISABLED; | 106 | set_irq_chip(i, &ioasic_irq_type); |
145 | irq_desc[i].action = 0; | 107 | for (; i < base + IO_IRQ_LINES; i++) |
146 | irq_desc[i].depth = 1; | 108 | set_irq_chip(i, &ioasic_dma_irq_type); |
147 | irq_desc[i].chip = &ioasic_irq_type; | ||
148 | } | ||
149 | for (; i < base + IO_IRQ_LINES; i++) { | ||
150 | irq_desc[i].status = IRQ_DISABLED; | ||
151 | irq_desc[i].action = 0; | ||
152 | irq_desc[i].depth = 1; | ||
153 | irq_desc[i].chip = &ioasic_dma_irq_type; | ||
154 | } | ||
155 | 109 | ||
156 | ioasic_irq_base = base; | 110 | ioasic_irq_base = base; |
157 | } | 111 | } |
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index 04a367a60a57..c761d97787ec 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c | |||
@@ -14,7 +14,6 @@ | |||
14 | 14 | ||
15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
16 | #include <linux/irq.h> | 16 | #include <linux/irq.h> |
17 | #include <linux/spinlock.h> | ||
18 | #include <linux/types.h> | 17 | #include <linux/types.h> |
19 | 18 | ||
20 | #include <asm/dec/kn02.h> | 19 | #include <asm/dec/kn02.h> |
@@ -29,7 +28,6 @@ | |||
29 | * There is no default value -- it has to be initialized. | 28 | * There is no default value -- it has to be initialized. |
30 | */ | 29 | */ |
31 | u32 cached_kn02_csr; | 30 | u32 cached_kn02_csr; |
32 | DEFINE_SPINLOCK(kn02_lock); | ||
33 | 31 | ||
34 | 32 | ||
35 | static int kn02_irq_base; | 33 | static int kn02_irq_base; |
@@ -53,54 +51,24 @@ static inline void mask_kn02_irq(unsigned int irq) | |||
53 | *csr = cached_kn02_csr; | 51 | *csr = cached_kn02_csr; |
54 | } | 52 | } |
55 | 53 | ||
56 | static inline void enable_kn02_irq(unsigned int irq) | ||
57 | { | ||
58 | unsigned long flags; | ||
59 | |||
60 | spin_lock_irqsave(&kn02_lock, flags); | ||
61 | unmask_kn02_irq(irq); | ||
62 | spin_unlock_irqrestore(&kn02_lock, flags); | ||
63 | } | ||
64 | |||
65 | static inline void disable_kn02_irq(unsigned int irq) | ||
66 | { | ||
67 | unsigned long flags; | ||
68 | |||
69 | spin_lock_irqsave(&kn02_lock, flags); | ||
70 | mask_kn02_irq(irq); | ||
71 | spin_unlock_irqrestore(&kn02_lock, flags); | ||
72 | } | ||
73 | |||
74 | |||
75 | static unsigned int startup_kn02_irq(unsigned int irq) | ||
76 | { | ||
77 | enable_kn02_irq(irq); | ||
78 | return 0; | ||
79 | } | ||
80 | |||
81 | #define shutdown_kn02_irq disable_kn02_irq | ||
82 | |||
83 | static void ack_kn02_irq(unsigned int irq) | 54 | static void ack_kn02_irq(unsigned int irq) |
84 | { | 55 | { |
85 | spin_lock(&kn02_lock); | ||
86 | mask_kn02_irq(irq); | 56 | mask_kn02_irq(irq); |
87 | spin_unlock(&kn02_lock); | ||
88 | iob(); | 57 | iob(); |
89 | } | 58 | } |
90 | 59 | ||
91 | static void end_kn02_irq(unsigned int irq) | 60 | static void end_kn02_irq(unsigned int irq) |
92 | { | 61 | { |
93 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | 62 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
94 | enable_kn02_irq(irq); | 63 | unmask_kn02_irq(irq); |
95 | } | 64 | } |
96 | 65 | ||
97 | static struct irq_chip kn02_irq_type = { | 66 | static struct irq_chip kn02_irq_type = { |
98 | .typename = "KN02-CSR", | 67 | .typename = "KN02-CSR", |
99 | .startup = startup_kn02_irq, | ||
100 | .shutdown = shutdown_kn02_irq, | ||
101 | .enable = enable_kn02_irq, | ||
102 | .disable = disable_kn02_irq, | ||
103 | .ack = ack_kn02_irq, | 68 | .ack = ack_kn02_irq, |
69 | .mask = mask_kn02_irq, | ||
70 | .mask_ack = ack_kn02_irq, | ||
71 | .unmask = unmask_kn02_irq, | ||
104 | .end = end_kn02_irq, | 72 | .end = end_kn02_irq, |
105 | }; | 73 | }; |
106 | 74 | ||
@@ -109,22 +77,15 @@ void __init init_kn02_irqs(int base) | |||
109 | { | 77 | { |
110 | volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + | 78 | volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + |
111 | KN02_CSR); | 79 | KN02_CSR); |
112 | unsigned long flags; | ||
113 | int i; | 80 | int i; |
114 | 81 | ||
115 | /* Mask interrupts. */ | 82 | /* Mask interrupts. */ |
116 | spin_lock_irqsave(&kn02_lock, flags); | ||
117 | cached_kn02_csr &= ~KN02_CSR_IOINTEN; | 83 | cached_kn02_csr &= ~KN02_CSR_IOINTEN; |
118 | *csr = cached_kn02_csr; | 84 | *csr = cached_kn02_csr; |
119 | iob(); | 85 | iob(); |
120 | spin_unlock_irqrestore(&kn02_lock, flags); | 86 | |
121 | 87 | for (i = base; i < base + KN02_IRQ_LINES; i++) | |
122 | for (i = base; i < base + KN02_IRQ_LINES; i++) { | 88 | set_irq_chip(i, &kn02_irq_type); |
123 | irq_desc[i].status = IRQ_DISABLED; | ||
124 | irq_desc[i].action = 0; | ||
125 | irq_desc[i].depth = 1; | ||
126 | irq_desc[i].chip = &kn02_irq_type; | ||
127 | } | ||
128 | 89 | ||
129 | kn02_irq_base = base; | 90 | kn02_irq_base = base; |
130 | } | 91 | } |