6 files changed, 31 insertions, 114 deletions

diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 3e374d05978f..c8430c07355e 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -18,7 +18,6 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
-#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include <asm/addrspace.h>
@@ -231,13 +230,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
 static inline void dec_kn02_be_init(void)
 {
         volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
-        unsigned long flags;
 
         kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
         kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
 
-        spin_lock_irqsave(&kn02_lock, flags);
-
         /* Preset write-only bits of the Control Register cache. */
         cached_kn02_csr = *csr | KN02_CSR_LEDS;
 
@@ -247,8 +243,6 @@ static inline void dec_kn02_be_init(void)
         cached_kn02_csr |= KN02_CSR_CORRECT;
         *csr = cached_kn02_csr;
         iob();
-
-        spin_unlock_irqrestore(&kn02_lock, flags);
 }
 
 static inline void dec_kn03_be_init(void)
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index 31dd47d1002d..b251ef864c33 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -267,7 +267,7 @@ handle_it:
                 LONG_L  s0, TI_REGS($28)
                 LONG_S  sp, TI_REGS($28)
                 PTR_LA  ra, ret_from_irq
-                j       do_IRQ
+                j       dec_irq_dispatch
                  nop
 
 #ifdef CONFIG_32BIT
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 41cd2a96148b..269b22b34313 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -13,7 +13,6 @@
 
 #include <linux/init.h>
 #include <linux/irq.h>
-#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include <asm/dec/ioasic.h>
@@ -21,8 +20,6 @@
 #include <asm/dec/ioasic_ints.h>
 
 
-static DEFINE_SPINLOCK(ioasic_lock);
-
 static int ioasic_irq_base;
 
 
@@ -52,65 +49,31 @@ static inline void clear_ioasic_irq(unsigned int irq)
         ioasic_write(IO_REG_SIR, sir);
 }
 
-static inline void enable_ioasic_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&ioasic_lock, flags);
-        unmask_ioasic_irq(irq);
-        spin_unlock_irqrestore(&ioasic_lock, flags);
-}
-
-static inline void disable_ioasic_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&ioasic_lock, flags);
-        mask_ioasic_irq(irq);
-        spin_unlock_irqrestore(&ioasic_lock, flags);
-}
-
-
-static inline unsigned int startup_ioasic_irq(unsigned int irq)
-{
-        enable_ioasic_irq(irq);
-        return 0;
-}
-
-#define shutdown_ioasic_irq disable_ioasic_irq
-
 static inline void ack_ioasic_irq(unsigned int irq)
 {
-        spin_lock(&ioasic_lock);
         mask_ioasic_irq(irq);
-        spin_unlock(&ioasic_lock);
         fast_iob();
 }
 
 static inline void end_ioasic_irq(unsigned int irq)
 {
         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-                enable_ioasic_irq(irq);
+                unmask_ioasic_irq(irq);
 }
 
 static struct irq_chip ioasic_irq_type = {
         .typename = "IO-ASIC",
-        .startup = startup_ioasic_irq,
-        .shutdown = shutdown_ioasic_irq,
-        .enable = enable_ioasic_irq,
-        .disable = disable_ioasic_irq,
         .ack = ack_ioasic_irq,
+        .mask = mask_ioasic_irq,
+        .mask_ack = ack_ioasic_irq,
+        .unmask = unmask_ioasic_irq,
         .end = end_ioasic_irq,
 };
 
 
-#define startup_ioasic_dma_irq startup_ioasic_irq
-
-#define shutdown_ioasic_dma_irq shutdown_ioasic_irq
-
-#define enable_ioasic_dma_irq enable_ioasic_irq
+#define unmask_ioasic_dma_irq unmask_ioasic_irq
 
-#define disable_ioasic_dma_irq disable_ioasic_irq
+#define mask_ioasic_dma_irq mask_ioasic_irq
 
 #define ack_ioasic_dma_irq ack_ioasic_irq
 
@@ -123,11 +86,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq)
 
 static struct irq_chip ioasic_dma_irq_type = {
         .typename = "IO-ASIC-DMA",
-        .startup = startup_ioasic_dma_irq,
-        .shutdown = shutdown_ioasic_dma_irq,
-        .enable = enable_ioasic_dma_irq,
-        .disable = disable_ioasic_dma_irq,
         .ack = ack_ioasic_dma_irq,
+        .mask = mask_ioasic_dma_irq,
+        .mask_ack = ack_ioasic_dma_irq,
+        .unmask = unmask_ioasic_dma_irq,
         .end = end_ioasic_dma_irq,
 };
 
@@ -140,18 +102,12 @@ void __init init_ioasic_irqs(int base)
         ioasic_write(IO_REG_SIMR, 0);
         fast_iob();
 
-        for (i = base; i < base + IO_INR_DMA; i++) {
-                irq_desc[i].status = IRQ_DISABLED;
-                irq_desc[i].action = 0;
-                irq_desc[i].depth = 1;
-                irq_desc[i].chip = &ioasic_irq_type;
-        }
-        for (; i < base + IO_IRQ_LINES; i++) {
-                irq_desc[i].status = IRQ_DISABLED;
-                irq_desc[i].action = 0;
-                irq_desc[i].depth = 1;
-                irq_desc[i].chip = &ioasic_dma_irq_type;
-        }
+        for (i = base; i < base + IO_INR_DMA; i++)
+                set_irq_chip_and_handler(i, &ioasic_irq_type,
+                                         handle_level_irq);
+        for (; i < base + IO_IRQ_LINES; i++)
+                set_irq_chip_and_handler(i, &ioasic_dma_irq_type,
+                                         handle_level_irq);
 
         ioasic_irq_base = base;
 }
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 04a367a60a57..5a9be4c93584 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -14,7 +14,6 @@
 
 #include <linux/init.h>
 #include <linux/irq.h>
-#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include <asm/dec/kn02.h>
@@ -29,7 +28,6 @@
  * There is no default value -- it has to be initialized.
  */
 u32 cached_kn02_csr;
-DEFINE_SPINLOCK(kn02_lock);
 
 
 static int kn02_irq_base;
@@ -53,54 +51,24 @@ static inline void mask_kn02_irq(unsigned int irq)
         *csr = cached_kn02_csr;
 }
 
-static inline void enable_kn02_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&kn02_lock, flags);
-        unmask_kn02_irq(irq);
-        spin_unlock_irqrestore(&kn02_lock, flags);
-}
-
-static inline void disable_kn02_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&kn02_lock, flags);
-        mask_kn02_irq(irq);
-        spin_unlock_irqrestore(&kn02_lock, flags);
-}
-
-
-static unsigned int startup_kn02_irq(unsigned int irq)
-{
-        enable_kn02_irq(irq);
-        return 0;
-}
-
-#define shutdown_kn02_irq disable_kn02_irq
-
 static void ack_kn02_irq(unsigned int irq)
 {
-        spin_lock(&kn02_lock);
         mask_kn02_irq(irq);
-        spin_unlock(&kn02_lock);
         iob();
 }
 
 static void end_kn02_irq(unsigned int irq)
 {
         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-                enable_kn02_irq(irq);
+                unmask_kn02_irq(irq);
 }
 
 static struct irq_chip kn02_irq_type = {
         .typename = "KN02-CSR",
-        .startup = startup_kn02_irq,
-        .shutdown = shutdown_kn02_irq,
-        .enable = enable_kn02_irq,
-        .disable = disable_kn02_irq,
         .ack = ack_kn02_irq,
+        .mask = mask_kn02_irq,
+        .mask_ack = ack_kn02_irq,
+        .unmask = unmask_kn02_irq,
         .end = end_kn02_irq,
 };
 
@@ -109,22 +77,15 @@ void __init init_kn02_irqs(int base)
 {
         volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
                                                        KN02_CSR);
-        unsigned long flags;
         int i;
 
         /* Mask interrupts. */
-        spin_lock_irqsave(&kn02_lock, flags);
         cached_kn02_csr &= ~KN02_CSR_IOINTEN;
         *csr = cached_kn02_csr;
         iob();
-        spin_unlock_irqrestore(&kn02_lock, flags);
-
-        for (i = base; i < base + KN02_IRQ_LINES; i++) {
-                irq_desc[i].status = IRQ_DISABLED;
-                irq_desc[i].action = 0;
-                irq_desc[i].depth = 1;
-                irq_desc[i].chip = &kn02_irq_type;
-        }
+
+        for (i = base; i < base + KN02_IRQ_LINES; i++)
+                set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
 
         kn02_irq_base = base;
 }
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 6b7481e97bec..d34032ac492a 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -761,3 +761,9 @@ void __init arch_init_irq(void)
         if (dec_interrupt[DEC_IRQ_HALT] >= 0)
                 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
 }
+
+asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
+{
+        do_IRQ(irq);
+        return 0;
+}
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 69e424e9ab6f..8b7e0c17ac35 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -151,7 +151,7 @@ static void dec_timer_ack(void)
         CMOS_READ(RTC_REG_C);                   /* Ack the RTC interrupt.  */
 }
 
-static unsigned int dec_ioasic_hpt_read(void)
+static cycle_t dec_ioasic_hpt_read(void)
 {
         /*
          * The free-running counter is 32-bit which is good for about
@@ -171,7 +171,7 @@ void __init dec_time_init(void)
 
         if (!cpu_has_counter && IOASIC)
                 /* For pre-R4k systems we use the I/O ASIC's counter.  */
-                mips_hpt_read = dec_ioasic_hpt_read;
+                clocksource_mips.read = dec_ioasic_hpt_read;
 
         /* Set up the rate of periodic DS1287 interrupts.  */
         CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);