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-rw-r--r--arch/mips/dec/time.c9
1 files changed, 1 insertions, 8 deletions
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 4cf0c06e2414..69e424e9ab6f 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -160,11 +160,6 @@ static unsigned int dec_ioasic_hpt_read(void)
160 return ioasic_read(IO_REG_FCTR); 160 return ioasic_read(IO_REG_FCTR);
161} 161}
162 162
163static void dec_ioasic_hpt_init(unsigned int count)
164{
165 ioasic_write(IO_REG_FCTR, ioasic_read(IO_REG_FCTR) - count);
166}
167
168 163
169void __init dec_time_init(void) 164void __init dec_time_init(void)
170{ 165{
@@ -174,11 +169,9 @@ void __init dec_time_init(void)
174 mips_timer_state = dec_timer_state; 169 mips_timer_state = dec_timer_state;
175 mips_timer_ack = dec_timer_ack; 170 mips_timer_ack = dec_timer_ack;
176 171
177 if (!cpu_has_counter && IOASIC) { 172 if (!cpu_has_counter && IOASIC)
178 /* For pre-R4k systems we use the I/O ASIC's counter. */ 173 /* For pre-R4k systems we use the I/O ASIC's counter. */
179 mips_hpt_read = dec_ioasic_hpt_read; 174 mips_hpt_read = dec_ioasic_hpt_read;
180 mips_hpt_init = dec_ioasic_hpt_init;
181 }
182 175
183 /* Set up the rate of periodic DS1287 interrupts. */ 176 /* Set up the rate of periodic DS1287 interrupts. */
184 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A); 177 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);