diff options
Diffstat (limited to 'arch/mips/dec/setup.c')
-rw-r--r-- | arch/mips/dec/setup.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index d34032ac492a..b8a5e75ba0ab 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c | |||
@@ -53,6 +53,8 @@ unsigned long dec_kn_slot_base, dec_kn_slot_size; | |||
53 | EXPORT_SYMBOL(dec_kn_slot_base); | 53 | EXPORT_SYMBOL(dec_kn_slot_base); |
54 | EXPORT_SYMBOL(dec_kn_slot_size); | 54 | EXPORT_SYMBOL(dec_kn_slot_size); |
55 | 55 | ||
56 | int dec_tc_bus; | ||
57 | |||
56 | spinlock_t ioasic_ssr_lock; | 58 | spinlock_t ioasic_ssr_lock; |
57 | 59 | ||
58 | volatile u32 *ioasic_base; | 60 | volatile u32 *ioasic_base; |
@@ -234,7 +236,7 @@ static void __init dec_init_kn01(void) | |||
234 | memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, | 236 | memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, |
235 | sizeof(kn01_cpu_mask_nr_tbl)); | 237 | sizeof(kn01_cpu_mask_nr_tbl)); |
236 | 238 | ||
237 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 239 | mips_cpu_irq_init(); |
238 | 240 | ||
239 | } /* dec_init_kn01 */ | 241 | } /* dec_init_kn01 */ |
240 | 242 | ||
@@ -309,7 +311,7 @@ static void __init dec_init_kn230(void) | |||
309 | memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, | 311 | memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, |
310 | sizeof(kn230_cpu_mask_nr_tbl)); | 312 | sizeof(kn230_cpu_mask_nr_tbl)); |
311 | 313 | ||
312 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 314 | mips_cpu_irq_init(); |
313 | 315 | ||
314 | } /* dec_init_kn230 */ | 316 | } /* dec_init_kn230 */ |
315 | 317 | ||
@@ -403,7 +405,7 @@ static void __init dec_init_kn02(void) | |||
403 | memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, | 405 | memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, |
404 | sizeof(kn02_asic_mask_nr_tbl)); | 406 | sizeof(kn02_asic_mask_nr_tbl)); |
405 | 407 | ||
406 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 408 | mips_cpu_irq_init(); |
407 | init_kn02_irqs(KN02_IRQ_BASE); | 409 | init_kn02_irqs(KN02_IRQ_BASE); |
408 | 410 | ||
409 | } /* dec_init_kn02 */ | 411 | } /* dec_init_kn02 */ |
@@ -504,7 +506,7 @@ static void __init dec_init_kn02ba(void) | |||
504 | memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, | 506 | memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, |
505 | sizeof(kn02ba_asic_mask_nr_tbl)); | 507 | sizeof(kn02ba_asic_mask_nr_tbl)); |
506 | 508 | ||
507 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 509 | mips_cpu_irq_init(); |
508 | init_ioasic_irqs(IO_IRQ_BASE); | 510 | init_ioasic_irqs(IO_IRQ_BASE); |
509 | 511 | ||
510 | } /* dec_init_kn02ba */ | 512 | } /* dec_init_kn02ba */ |
@@ -601,7 +603,7 @@ static void __init dec_init_kn02ca(void) | |||
601 | memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, | 603 | memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, |
602 | sizeof(kn02ca_asic_mask_nr_tbl)); | 604 | sizeof(kn02ca_asic_mask_nr_tbl)); |
603 | 605 | ||
604 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 606 | mips_cpu_irq_init(); |
605 | init_ioasic_irqs(IO_IRQ_BASE); | 607 | init_ioasic_irqs(IO_IRQ_BASE); |
606 | 608 | ||
607 | } /* dec_init_kn02ca */ | 609 | } /* dec_init_kn02ca */ |
@@ -702,7 +704,7 @@ static void __init dec_init_kn03(void) | |||
702 | memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, | 704 | memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, |
703 | sizeof(kn03_asic_mask_nr_tbl)); | 705 | sizeof(kn03_asic_mask_nr_tbl)); |
704 | 706 | ||
705 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 707 | mips_cpu_irq_init(); |
706 | init_ioasic_irqs(IO_IRQ_BASE); | 708 | init_ioasic_irqs(IO_IRQ_BASE); |
707 | 709 | ||
708 | } /* dec_init_kn03 */ | 710 | } /* dec_init_kn03 */ |