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-rw-r--r--arch/mips/dec/kn01-berr.c201
1 files changed, 201 insertions, 0 deletions
diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c
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1/*
2 * linux/arch/mips/dec/kn01-berr.c
3 *
4 * Bus error event handling code for DECstation/DECsystem 3100
5 * and 2100 (KN01) systems equipped with parity error detection
6 * logic.
7 *
8 * Copyright (c) 2005 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/spinlock.h>
20#include <linux/types.h>
21
22#include <asm/inst.h>
23#include <asm/mipsregs.h>
24#include <asm/page.h>
25#include <asm/system.h>
26#include <asm/traps.h>
27#include <asm/uaccess.h>
28
29#include <asm/dec/kn01.h>
30
31
32/* CP0 hazard avoidance. */
33#define BARRIER \
34 __asm__ __volatile__( \
35 ".set push\n\t" \
36 ".set noreorder\n\t" \
37 "nop\n\t" \
38 ".set pop\n\t")
39
40/*
41 * Bits 7:0 of the Control Register are write-only -- the
42 * corresponding bits of the Status Register have a different
43 * meaning. Hence we use a cache. It speeds up things a bit
44 * as well.
45 *
46 * There is no default value -- it has to be initialized.
47 */
48u16 cached_kn01_csr;
49DEFINE_SPINLOCK(kn01_lock);
50
51
52static inline void dec_kn01_be_ack(void)
53{
54 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
55 unsigned long flags;
56
57 spin_lock_irqsave(&kn01_lock, flags);
58
59 *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */
60 iob();
61
62 spin_unlock_irqrestore(&kn01_lock, flags);
63}
64
65static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
66{
67 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
68 KN01_ERRADDR);
69
70 static const char excstr[] = "exception";
71 static const char intstr[] = "interrupt";
72 static const char cpustr[] = "CPU";
73 static const char mreadstr[] = "memory read";
74 static const char readstr[] = "read";
75 static const char writestr[] = "write";
76 static const char timestr[] = "timeout";
77 static const char paritystr[] = "parity error";
78
79 int data = regs->cp0_cause & 4;
80 unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc +
81 ((regs->cp0_cause & CAUSEF_BD) != 0);
82 union mips_instruction insn;
83 unsigned long entrylo, offset;
84 long asid, entryhi, vaddr;
85
86 const char *kind, *agent, *cycle, *event;
87 unsigned long address;
88
89 u32 erraddr = *kn01_erraddr;
90 int action = MIPS_BE_FATAL;
91
92 /* Ack ASAP, so that any subsequent errors get caught. */
93 dec_kn01_be_ack();
94
95 kind = invoker ? intstr : excstr;
96
97 agent = cpustr;
98
99 if (invoker)
100 address = erraddr;
101 else {
102 /* Bloody hardware doesn't record the address for reads... */
103 if (data) {
104 /* This never faults. */
105 __get_user(insn.word, pc);
106 vaddr = regs->regs[insn.i_format.rs] +
107 insn.i_format.simmediate;
108 } else
109 vaddr = (long)pc;
110 if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1)
111 address = CPHYSADDR(vaddr);
112 else {
113 /* Peek at what physical address the CPU used. */
114 asid = read_c0_entryhi();
115 entryhi = asid & (PAGE_SIZE - 1);
116 entryhi |= vaddr & ~(PAGE_SIZE - 1);
117 write_c0_entryhi(entryhi);
118 BARRIER;
119 tlb_probe();
120 /* No need to check for presence. */
121 tlb_read();
122 entrylo = read_c0_entrylo0();
123 write_c0_entryhi(asid);
124 offset = vaddr & (PAGE_SIZE - 1);
125 address = (entrylo & ~(PAGE_SIZE - 1)) | offset;
126 }
127 }
128
129 /* Treat low 256MB as memory, high -- as I/O. */
130 if (address < 0x10000000) {
131 cycle = mreadstr;
132 event = paritystr;
133 } else {
134 cycle = invoker ? writestr : readstr;
135 event = timestr;
136 }
137
138 if (is_fixup)
139 action = MIPS_BE_FIXUP;
140
141 if (action != MIPS_BE_FIXUP)
142 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
143 kind, agent, cycle, event, address);
144
145 return action;
146}
147
148int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
149{
150 return dec_kn01_be_backend(regs, is_fixup, 0);
151}
152
153irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
154 struct pt_regs *regs)
155{
156 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
157 int action;
158
159 if (!(*csr & KN01_CSR_MEMERR))
160 return IRQ_NONE; /* Must have been video. */
161
162 action = dec_kn01_be_backend(regs, 0, 1);
163
164 if (action == MIPS_BE_DISCARD)
165 return IRQ_HANDLED;
166
167 /*
168 * FIXME: Find the affected processes and kill them, otherwise
169 * we must die.
170 *
171 * The interrupt is asynchronously delivered thus EPC and RA
172 * may be irrelevant, but are printed for a reference.
173 */
174 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
175 regs->cp0_epc, regs->regs[31]);
176 die("Unrecoverable bus error", regs);
177}
178
179
180void __init dec_kn01_be_init(void)
181{
182 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
183 unsigned long flags;
184
185 spin_lock_irqsave(&kn01_lock, flags);
186
187 /* Preset write-only bits of the Control Register cache. */
188 cached_kn01_csr = *csr;
189 cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS;
190 cached_kn01_csr |= KN01_CSR_LEDS;
191
192 /* Enable parity error detection. */
193 cached_kn01_csr &= ~KN01_CSR_PARDIS;
194 *csr = cached_kn01_csr;
195 iob();
196
197 spin_unlock_irqrestore(&kn01_lock, flags);
198
199 /* Clear any leftover errors from the firmware. */
200 dec_kn01_be_ack();
201}
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