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Diffstat (limited to 'arch/mips/dec/ioasic-irq.c')
-rw-r--r--arch/mips/dec/ioasic-irq.c64
1 files changed, 16 insertions, 48 deletions
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index cb41954fc321..824e08c73798 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -17,80 +17,48 @@
17#include <asm/dec/ioasic_addrs.h> 17#include <asm/dec/ioasic_addrs.h>
18#include <asm/dec/ioasic_ints.h> 18#include <asm/dec/ioasic_ints.h>
19 19
20
21static int ioasic_irq_base; 20static int ioasic_irq_base;
22 21
23 22static void unmask_ioasic_irq(struct irq_data *d)
24static inline void unmask_ioasic_irq(unsigned int irq)
25{ 23{
26 u32 simr; 24 u32 simr;
27 25
28 simr = ioasic_read(IO_REG_SIMR); 26 simr = ioasic_read(IO_REG_SIMR);
29 simr |= (1 << (irq - ioasic_irq_base)); 27 simr |= (1 << (d->irq - ioasic_irq_base));
30 ioasic_write(IO_REG_SIMR, simr); 28 ioasic_write(IO_REG_SIMR, simr);
31} 29}
32 30
33static inline void mask_ioasic_irq(unsigned int irq) 31static void mask_ioasic_irq(struct irq_data *d)
34{ 32{
35 u32 simr; 33 u32 simr;
36 34
37 simr = ioasic_read(IO_REG_SIMR); 35 simr = ioasic_read(IO_REG_SIMR);
38 simr &= ~(1 << (irq - ioasic_irq_base)); 36 simr &= ~(1 << (d->irq - ioasic_irq_base));
39 ioasic_write(IO_REG_SIMR, simr); 37 ioasic_write(IO_REG_SIMR, simr);
40} 38}
41 39
42static inline void clear_ioasic_irq(unsigned int irq) 40static void ack_ioasic_irq(struct irq_data *d)
43{ 41{
44 u32 sir; 42 mask_ioasic_irq(d);
45
46 sir = ~(1 << (irq - ioasic_irq_base));
47 ioasic_write(IO_REG_SIR, sir);
48}
49
50static inline void ack_ioasic_irq(unsigned int irq)
51{
52 mask_ioasic_irq(irq);
53 fast_iob(); 43 fast_iob();
54} 44}
55 45
56static inline void end_ioasic_irq(unsigned int irq)
57{
58 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
59 unmask_ioasic_irq(irq);
60}
61
62static struct irq_chip ioasic_irq_type = { 46static struct irq_chip ioasic_irq_type = {
63 .name = "IO-ASIC", 47 .name = "IO-ASIC",
64 .ack = ack_ioasic_irq, 48 .irq_ack = ack_ioasic_irq,
65 .mask = mask_ioasic_irq, 49 .irq_mask = mask_ioasic_irq,
66 .mask_ack = ack_ioasic_irq, 50 .irq_mask_ack = ack_ioasic_irq,
67 .unmask = unmask_ioasic_irq, 51 .irq_unmask = unmask_ioasic_irq,
68}; 52};
69 53
70
71#define unmask_ioasic_dma_irq unmask_ioasic_irq
72
73#define mask_ioasic_dma_irq mask_ioasic_irq
74
75#define ack_ioasic_dma_irq ack_ioasic_irq
76
77static inline void end_ioasic_dma_irq(unsigned int irq)
78{
79 clear_ioasic_irq(irq);
80 fast_iob();
81 end_ioasic_irq(irq);
82}
83
84static struct irq_chip ioasic_dma_irq_type = { 54static struct irq_chip ioasic_dma_irq_type = {
85 .name = "IO-ASIC-DMA", 55 .name = "IO-ASIC-DMA",
86 .ack = ack_ioasic_dma_irq, 56 .irq_ack = ack_ioasic_irq,
87 .mask = mask_ioasic_dma_irq, 57 .irq_mask = mask_ioasic_irq,
88 .mask_ack = ack_ioasic_dma_irq, 58 .irq_mask_ack = ack_ioasic_irq,
89 .unmask = unmask_ioasic_dma_irq, 59 .irq_unmask = unmask_ioasic_irq,
90 .end = end_ioasic_dma_irq,
91}; 60};
92 61
93
94void __init init_ioasic_irqs(int base) 62void __init init_ioasic_irqs(int base)
95{ 63{
96 int i; 64 int i;
@@ -100,10 +68,10 @@ void __init init_ioasic_irqs(int base)
100 fast_iob(); 68 fast_iob();
101 69
102 for (i = base; i < base + IO_INR_DMA; i++) 70 for (i = base; i < base + IO_INR_DMA; i++)
103 set_irq_chip_and_handler(i, &ioasic_irq_type, 71 irq_set_chip_and_handler(i, &ioasic_irq_type,
104 handle_level_irq); 72 handle_level_irq);
105 for (; i < base + IO_IRQ_LINES; i++) 73 for (; i < base + IO_IRQ_LINES; i++)
106 set_irq_chip(i, &ioasic_dma_irq_type); 74 irq_set_chip(i, &ioasic_dma_irq_type);
107 75
108 ioasic_irq_base = base; 76 ioasic_irq_base = base;
109} 77}