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Diffstat (limited to 'arch/mips/dec/ioasic-irq.c')
-rw-r--r--arch/mips/dec/ioasic-irq.c72
1 files changed, 13 insertions, 59 deletions
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 41cd2a96148b..d0af08bdbb4e 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -13,7 +13,6 @@
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/spinlock.h>
17#include <linux/types.h> 16#include <linux/types.h>
18 17
19#include <asm/dec/ioasic.h> 18#include <asm/dec/ioasic.h>
@@ -21,8 +20,6 @@
21#include <asm/dec/ioasic_ints.h> 20#include <asm/dec/ioasic_ints.h>
22 21
23 22
24static DEFINE_SPINLOCK(ioasic_lock);
25
26static int ioasic_irq_base; 23static int ioasic_irq_base;
27 24
28 25
@@ -52,65 +49,31 @@ static inline void clear_ioasic_irq(unsigned int irq)
52 ioasic_write(IO_REG_SIR, sir); 49 ioasic_write(IO_REG_SIR, sir);
53} 50}
54 51
55static inline void enable_ioasic_irq(unsigned int irq)
56{
57 unsigned long flags;
58
59 spin_lock_irqsave(&ioasic_lock, flags);
60 unmask_ioasic_irq(irq);
61 spin_unlock_irqrestore(&ioasic_lock, flags);
62}
63
64static inline void disable_ioasic_irq(unsigned int irq)
65{
66 unsigned long flags;
67
68 spin_lock_irqsave(&ioasic_lock, flags);
69 mask_ioasic_irq(irq);
70 spin_unlock_irqrestore(&ioasic_lock, flags);
71}
72
73
74static inline unsigned int startup_ioasic_irq(unsigned int irq)
75{
76 enable_ioasic_irq(irq);
77 return 0;
78}
79
80#define shutdown_ioasic_irq disable_ioasic_irq
81
82static inline void ack_ioasic_irq(unsigned int irq) 52static inline void ack_ioasic_irq(unsigned int irq)
83{ 53{
84 spin_lock(&ioasic_lock);
85 mask_ioasic_irq(irq); 54 mask_ioasic_irq(irq);
86 spin_unlock(&ioasic_lock);
87 fast_iob(); 55 fast_iob();
88} 56}
89 57
90static inline void end_ioasic_irq(unsigned int irq) 58static inline void end_ioasic_irq(unsigned int irq)
91{ 59{
92 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 60 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
93 enable_ioasic_irq(irq); 61 unmask_ioasic_irq(irq);
94} 62}
95 63
96static struct irq_chip ioasic_irq_type = { 64static struct irq_chip ioasic_irq_type = {
97 .typename = "IO-ASIC", 65 .typename = "IO-ASIC",
98 .startup = startup_ioasic_irq,
99 .shutdown = shutdown_ioasic_irq,
100 .enable = enable_ioasic_irq,
101 .disable = disable_ioasic_irq,
102 .ack = ack_ioasic_irq, 66 .ack = ack_ioasic_irq,
67 .mask = mask_ioasic_irq,
68 .mask_ack = ack_ioasic_irq,
69 .unmask = unmask_ioasic_irq,
103 .end = end_ioasic_irq, 70 .end = end_ioasic_irq,
104}; 71};
105 72
106 73
107#define startup_ioasic_dma_irq startup_ioasic_irq 74#define unmask_ioasic_dma_irq unmask_ioasic_irq
108
109#define shutdown_ioasic_dma_irq shutdown_ioasic_irq
110
111#define enable_ioasic_dma_irq enable_ioasic_irq
112 75
113#define disable_ioasic_dma_irq disable_ioasic_irq 76#define mask_ioasic_dma_irq mask_ioasic_irq
114 77
115#define ack_ioasic_dma_irq ack_ioasic_irq 78#define ack_ioasic_dma_irq ack_ioasic_irq
116 79
@@ -123,11 +86,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq)
123 86
124static struct irq_chip ioasic_dma_irq_type = { 87static struct irq_chip ioasic_dma_irq_type = {
125 .typename = "IO-ASIC-DMA", 88 .typename = "IO-ASIC-DMA",
126 .startup = startup_ioasic_dma_irq,
127 .shutdown = shutdown_ioasic_dma_irq,
128 .enable = enable_ioasic_dma_irq,
129 .disable = disable_ioasic_dma_irq,
130 .ack = ack_ioasic_dma_irq, 89 .ack = ack_ioasic_dma_irq,
90 .mask = mask_ioasic_dma_irq,
91 .mask_ack = ack_ioasic_dma_irq,
92 .unmask = unmask_ioasic_dma_irq,
131 .end = end_ioasic_dma_irq, 93 .end = end_ioasic_dma_irq,
132}; 94};
133 95
@@ -140,18 +102,10 @@ void __init init_ioasic_irqs(int base)
140 ioasic_write(IO_REG_SIMR, 0); 102 ioasic_write(IO_REG_SIMR, 0);
141 fast_iob(); 103 fast_iob();
142 104
143 for (i = base; i < base + IO_INR_DMA; i++) { 105 for (i = base; i < base + IO_INR_DMA; i++)
144 irq_desc[i].status = IRQ_DISABLED; 106 set_irq_chip(i, &ioasic_irq_type);
145 irq_desc[i].action = 0; 107 for (; i < base + IO_IRQ_LINES; i++)
146 irq_desc[i].depth = 1; 108 set_irq_chip(i, &ioasic_dma_irq_type);
147 irq_desc[i].chip = &ioasic_irq_type;
148 }
149 for (; i < base + IO_IRQ_LINES; i++) {
150 irq_desc[i].status = IRQ_DISABLED;
151 irq_desc[i].action = 0;
152 irq_desc[i].depth = 1;
153 irq_desc[i].chip = &ioasic_dma_irq_type;
154 }
155 109
156 ioasic_irq_base = base; 110 ioasic_irq_base = base;
157} 111}