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-rw-r--r--arch/mips/dec/ecc-berr.c280
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diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
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1/*
2 * linux/arch/mips/dec/ecc-berr.c
3 *
4 * Bus error event handling code for systems equipped with ECC
5 * handling logic, i.e. DECstation/DECsystem 5000/200 (KN02),
6 * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
7 * 5900/260 (KN05) systems.
8 *
9 * Copyright (c) 2003 Maciej W. Rozycki
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/spinlock.h>
21#include <linux/types.h>
22
23#include <asm/addrspace.h>
24#include <asm/bootinfo.h>
25#include <asm/cpu.h>
26#include <asm/processor.h>
27#include <asm/system.h>
28#include <asm/traps.h>
29
30#include <asm/dec/ecc.h>
31#include <asm/dec/kn02.h>
32#include <asm/dec/kn03.h>
33#include <asm/dec/kn05.h>
34
35static volatile u32 *kn0x_erraddr;
36static volatile u32 *kn0x_chksyn;
37
38static inline void dec_ecc_be_ack(void)
39{
40 *kn0x_erraddr = 0; /* any write clears the IRQ */
41 iob();
42}
43
44static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
45{
46 static const char excstr[] = "exception";
47 static const char intstr[] = "interrupt";
48 static const char cpustr[] = "CPU";
49 static const char dmastr[] = "DMA";
50 static const char readstr[] = "read";
51 static const char mreadstr[] = "memory read";
52 static const char writestr[] = "write";
53 static const char mwritstr[] = "partial memory write";
54 static const char timestr[] = "timeout";
55 static const char overstr[] = "overrun";
56 static const char eccstr[] = "ECC error";
57
58 const char *kind, *agent, *cycle, *event;
59 const char *status = "", *xbit = "", *fmt = "";
60 dma_addr_t address;
61 u16 syn = 0, sngl;
62
63 int i = 0;
64
65 u32 erraddr = *kn0x_erraddr;
66 u32 chksyn = *kn0x_chksyn;
67 int action = MIPS_BE_FATAL;
68
69 /* For non-ECC ack ASAP, so any subsequent errors get caught. */
70 if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
71 dec_ecc_be_ack();
72
73 kind = invoker ? intstr : excstr;
74
75 if (!(erraddr & KN0X_EAR_VALID)) {
76 /* No idea what happened. */
77 printk(KERN_ALERT "Unidentified bus error %s.\n", kind);
78 return action;
79 }
80
81 agent = (erraddr & KN0X_EAR_CPU) ? cpustr : dmastr;
82
83 if (erraddr & KN0X_EAR_ECCERR) {
84 /* An ECC error on a CPU or DMA transaction. */
85 cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr;
86 event = eccstr;
87 } else {
88 /* A CPU timeout or a DMA overrun. */
89 cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr;
90 event = (erraddr & KN0X_EAR_CPU) ? timestr : overstr;
91 }
92
93 address = erraddr & KN0X_EAR_ADDRESS;
94 /* For ECC errors on reads adjust for MT pipelining. */
95 if ((erraddr & (KN0X_EAR_WRITE | KN0X_EAR_ECCERR)) == KN0X_EAR_ECCERR)
96 address = (address & ~0xfffLL) | ((address - 5) & 0xfffLL);
97 address <<= 2;
98
99 /* Only CPU errors are fixable. */
100 if (erraddr & KN0X_EAR_CPU && is_fixup)
101 action = MIPS_BE_FIXUP;
102
103 if (erraddr & KN0X_EAR_ECCERR) {
104 static const u8 data_sbit[32] = {
105 0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d,
106 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34,
107 0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c,
108 0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75,
109 };
110 static const u8 data_mbit[25] = {
111 0x07, 0x0d, 0x1f,
112 0x2f, 0x32, 0x37, 0x38, 0x3b, 0x3d, 0x3e,
113 0x43, 0x45, 0x46, 0x49, 0x4c, 0x51, 0x5e,
114 0x61, 0x6e, 0x73, 0x76, 0x79, 0x7a, 0x7c, 0x7f,
115 };
116 static const char sbestr[] = "corrected single";
117 static const char dbestr[] = "uncorrectable double";
118 static const char mbestr[] = "uncorrectable multiple";
119
120 if (!(address & 0x4))
121 syn = chksyn; /* Low bank. */
122 else
123 syn = chksyn >> 16; /* High bank. */
124
125 if (!(syn & KN0X_ESR_VLDLO)) {
126 /* Ack now, no rewrite will happen. */
127 dec_ecc_be_ack();
128
129 fmt = KERN_ALERT "%s" "invalid.\n";
130 } else {
131 sngl = syn & KN0X_ESR_SNGLO;
132 syn &= KN0X_ESR_SYNLO;
133
134 /*
135 * Multibit errors may be tagged incorrectly;
136 * check the syndrome explicitly.
137 */
138 for (i = 0; i < 25; i++)
139 if (syn == data_mbit[i])
140 break;
141
142 if (i < 25) {
143 status = mbestr;
144 } else if (!sngl) {
145 status = dbestr;
146 } else {
147 volatile u32 *ptr = (void *)KSEG1ADDR(address);
148
149 *ptr = *ptr; /* Rewrite. */
150 iob();
151
152 status = sbestr;
153 action = MIPS_BE_DISCARD;
154 }
155
156 /* Ack now, now we've rewritten (or not). */
157 dec_ecc_be_ack();
158
159 if (syn && syn == (syn & -syn)) {
160 if (syn == 0x01) {
161 fmt = KERN_ALERT "%s"
162 "%#04x -- %s bit error "
163 "at check bit C%s.\n";
164 xbit = "X";
165 } else {
166 fmt = KERN_ALERT "%s"
167 "%#04x -- %s bit error "
168 "at check bit C%s%u.\n";
169 }
170 i = syn >> 2;
171 } else {
172 for (i = 0; i < 32; i++)
173 if (syn == data_sbit[i])
174 break;
175 if (i < 32)
176 fmt = KERN_ALERT "%s"
177 "%#04x -- %s bit error "
178 "at data bit D%s%u.\n";
179 else
180 fmt = KERN_ALERT "%s"
181 "%#04x -- %s bit error.\n";
182 }
183 }
184 }
185
186 if (action != MIPS_BE_FIXUP)
187 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx.\n",
188 kind, agent, cycle, event, address);
189
190 if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
191 printk(fmt, " ECC syndrome ", syn, status, xbit, i);
192
193 return action;
194}
195
196int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup)
197{
198 return dec_ecc_be_backend(regs, is_fixup, 0);
199}
200
201irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
202{
203 int action = dec_ecc_be_backend(regs, 0, 1);
204
205 if (action == MIPS_BE_DISCARD)
206 return IRQ_NONE;
207
208 /*
209 * FIXME: Find affected processes and kill them, otherwise we
210 * must die.
211 *
212 * The interrupt is asynchronously delivered thus EPC and RA
213 * may be irrelevant, but are printed for a reference.
214 */
215 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
216 regs->cp0_epc, regs->regs[31]);
217 die("Unrecoverable bus error", regs);
218}
219
220
221/*
222 * Initialization differs a bit between KN02 and KN03/KN05, so we
223 * need two variants. Once set up, all systems can be handled the
224 * same way.
225 */
226static inline void dec_kn02_be_init(void)
227{
228 volatile u32 *csr = (void *)KN02_CSR_BASE;
229 unsigned long flags;
230
231 kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR);
232 kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN);
233
234 spin_lock_irqsave(&kn02_lock, flags);
235
236 /* Preset write-only bits of the Control Register cache. */
237 cached_kn02_csr = *csr | KN03_CSR_LEDS;
238
239 /* Set normal ECC detection and generation. */
240 cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
241 /* Enable ECC correction. */
242 cached_kn02_csr |= KN02_CSR_CORRECT;
243 *csr = cached_kn02_csr;
244 iob();
245
246 spin_unlock_irqrestore(&kn02_lock, flags);
247}
248
249static inline void dec_kn03_be_init(void)
250{
251 volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR);
252 volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR);
253
254 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
255 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
256
257 /*
258 * Set normal ECC detection and generation, enable ECC correction.
259 * For KN05 we also need to make sure EE (?) is enabled in the MB.
260 * Otherwise DBE/IBE exceptions would be masked but bus error
261 * interrupts would still arrive, resulting in an inevitable crash
262 * if get_dbe() triggers one.
263 */
264 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
265 KN03_MCR_CORRECT;
266 if (current_cpu_data.cputype == CPU_R4400SC)
267 *mbcs |= KN05_MB_CSR_EE;
268 fast_iob();
269}
270
271void __init dec_ecc_be_init(void)
272{
273 if (mips_machtype == MACH_DS5000_200)
274 dec_kn02_be_init();
275 else
276 dec_kn03_be_init();
277
278 /* Clear any leftover errors from the firmware. */
279 dec_ecc_be_ack();
280}
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