aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/ddb5xxx
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/ddb5xxx')
-rw-r--r--arch/mips/ddb5xxx/common/prom.c8
-rw-r--r--arch/mips/ddb5xxx/ddb5074/Makefile8
-rw-r--r--arch/mips/ddb5xxx/ddb5074/irq.c169
-rw-r--r--arch/mips/ddb5xxx/ddb5074/nile4_pic.c286
-rw-r--r--arch/mips/ddb5xxx/ddb5074/setup.c234
-rw-r--r--arch/mips/ddb5xxx/ddb5476/Makefile9
-rw-r--r--arch/mips/ddb5xxx/ddb5476/dbg_io.c136
-rw-r--r--arch/mips/ddb5xxx/ddb5476/irq.c165
-rw-r--r--arch/mips/ddb5xxx/ddb5476/nile4_pic.c190
-rw-r--r--arch/mips/ddb5xxx/ddb5476/setup.c296
-rw-r--r--arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c109
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c2
12 files changed, 2 insertions, 1610 deletions
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c
index b8d1f7489f3b..00c62c1c28a3 100644
--- a/arch/mips/ddb5xxx/common/prom.c
+++ b/arch/mips/ddb5xxx/common/prom.c
@@ -56,13 +56,7 @@ void __init prom_init(void)
56 56
57 mips_machgroup = MACH_GROUP_NEC_DDB; 57 mips_machgroup = MACH_GROUP_NEC_DDB;
58 58
59#if defined(CONFIG_DDB5074) 59#if defined(CONFIG_DDB5477)
60 mips_machtype = MACH_NEC_DDB5074;
61 add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
62#elif defined(CONFIG_DDB5476)
63 mips_machtype = MACH_NEC_DDB5476;
64 add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
65#elif defined(CONFIG_DDB5477)
66 ddb5477_runtime_detection(); 60 ddb5477_runtime_detection();
67 add_memory_region(0, board_ram_size, BOOT_MEM_RAM); 61 add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
68#endif 62#endif
diff --git a/arch/mips/ddb5xxx/ddb5074/Makefile b/arch/mips/ddb5xxx/ddb5074/Makefile
deleted file mode 100644
index 304c02107b46..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines
3# under Linux.
4#
5
6obj-y += setup.o irq.o nile4_pic.o
7
8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5074/irq.c b/arch/mips/ddb5xxx/ddb5074/irq.c
deleted file mode 100644
index 60c087b7738c..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/irq.c
+++ /dev/null
@@ -1,169 +0,0 @@
1/*
2 * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/irq.h>
9#include <linux/signal.h>
10#include <linux/sched.h>
11#include <linux/types.h>
12#include <linux/interrupt.h>
13#include <linux/ioport.h>
14
15#include <asm/i8259.h>
16#include <asm/io.h>
17#include <asm/irq_cpu.h>
18#include <asm/ptrace.h>
19#include <asm/nile4.h>
20#include <asm/ddb5xxx/ddb5xxx.h>
21#include <asm/ddb5xxx/ddb5074.h>
22
23
24static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
25
26#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
27#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
28#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
29
30#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
31#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
32#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
33
34#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
35#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
36
37#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
38#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
39
40#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
41#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
42
43
44static void m1543_irq_setup(void)
45{
46 /*
47 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
48 * the possible IO sources in the M1543 are in use by us. We will
49 * use the following mapping:
50 *
51 * IRQ1 - keyboard (default set by M1543)
52 * IRQ3 - reserved for UART B (default set by M1543) (note that
53 * the schematics for the DDB Vrc-5074 board seem to
54 * indicate that IRQ3 is connected to the DS1386
55 * watchdog timer interrupt output so we might have
56 * a conflict)
57 * IRQ4 - reserved for UART A (default set by M1543)
58 * IRQ5 - parallel (default set by M1543)
59 * IRQ8 - DS1386 time of day (RTC) interrupt
60 * IRQ12 - mouse
61 */
62
63 /*
64 * Assing mouse interrupt to IRQ12
65 */
66
67 /* Enter configuration mode */
68 outb(0x51, M1543_PNP_CONFIG);
69 outb(0x23, M1543_PNP_CONFIG);
70
71 /* Select logical device 7 (Keyboard) */
72 outb(0x07, M1543_PNP_INDEX);
73 outb(0x07, M1543_PNP_DATA);
74
75 /* Select IRQ12 */
76 outb(0x72, M1543_PNP_INDEX);
77 outb(0x0c, M1543_PNP_DATA);
78
79 outb(0x30, M1543_PNP_INDEX);
80 printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
81
82 outb(0x70, M1543_PNP_INDEX);
83 printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
84
85 /* Leave configration mode */
86 outb(0xbb, M1543_PNP_CONFIG);
87
88
89}
90
91static void ddb_local0_irqdispatch(struct pt_regs *regs)
92{
93 u32 mask;
94 int nile4_irq;
95
96 mask = nile4_get_irq_stat(0);
97
98 /* Handle the timer interrupt first */
99#if 0
100 if (mask & (1 << NILE4_INT_GPT)) {
101 do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
102 mask &= ~(1 << NILE4_INT_GPT);
103 }
104#endif
105 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
106 if (mask & 1) {
107 if (nile4_irq == NILE4_INT_INTE) {
108 int i8259_irq;
109
110 nile4_clear_irq(NILE4_INT_INTE);
111 i8259_irq = nile4_i8259_iack();
112 do_IRQ(i8259_irq, regs);
113 } else
114 do_IRQ(nile4_to_irq(nile4_irq), regs);
115
116 }
117}
118
119static void ddb_local1_irqdispatch(void)
120{
121 printk("ddb_local1_irqdispatch called\n");
122}
123
124static void ddb_buserror_irq(void)
125{
126 printk("ddb_buserror_irq called\n");
127}
128
129static void ddb_8254timer_irq(void)
130{
131 printk("ddb_8254timer_irq called\n");
132}
133
134asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
135{
136 unsigned int pending = read_c0_cause() & read_c0_status();
137
138 if (pending & CAUSEF_IP2)
139 ddb_local0_irqdispatch(regs);
140 else if (pending & CAUSEF_IP3)
141 ddb_local1_irqdispatch();
142 else if (pending & CAUSEF_IP6)
143 ddb_buserror_irq();
144 else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
145 ddb_8254timer_irq();
146}
147
148void __init arch_init_irq(void)
149{
150 /* setup cascade interrupts */
151 setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
152 setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
153
154 nile4_irq_setup(NILE4_IRQ_BASE);
155 m1543_irq_setup();
156 init_i8259_irqs();
157
158
159 printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
160
161 mips_cpu_irq_init(CPU_IRQ_BASE);
162
163 printk("enabling 8259 cascade\n");
164
165 ddb5074_led_hex(0);
166
167 /* Enable the interrupt cascade */
168 nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
169}
diff --git a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
deleted file mode 100644
index 8743ffce8653..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
+++ /dev/null
@@ -1,286 +0,0 @@
1/*
2 * arch/mips/ddb5476/nile4.c --
3 * low-level PIC code for NEC Vrc-5476 (Nile 4)
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17
18#include <asm/addrspace.h>
19
20#include <asm/ddb5xxx/ddb5xxx.h>
21
22static int irq_base;
23
24/*
25 * Interrupt Programming
26 */
27void nile4_map_irq(int nile4_irq, int cpu_irq)
28{
29 u32 offset, t;
30
31 offset = DDB_INTCTRL;
32 if (nile4_irq >= 8) {
33 offset += 4;
34 nile4_irq -= 8;
35 }
36 t = ddb_in32(offset);
37 t &= ~(7 << (nile4_irq * 4));
38 t |= cpu_irq << (nile4_irq * 4);
39 ddb_out32(offset, t);
40}
41
42void nile4_map_irq_all(int cpu_irq)
43{
44 u32 all, t;
45
46 all = cpu_irq;
47 all |= all << 4;
48 all |= all << 8;
49 all |= all << 16;
50 t = ddb_in32(DDB_INTCTRL);
51 t &= 0x88888888;
52 t |= all;
53 ddb_out32(DDB_INTCTRL, t);
54 t = ddb_in32(DDB_INTCTRL + 4);
55 t &= 0x88888888;
56 t |= all;
57 ddb_out32(DDB_INTCTRL + 4, t);
58}
59
60void nile4_enable_irq(unsigned int nile4_irq)
61{
62 u32 offset, t;
63
64 nile4_irq-=irq_base;
65
66 ddb5074_led_hex(8);
67
68 offset = DDB_INTCTRL;
69 if (nile4_irq >= 8) {
70 offset += 4;
71 nile4_irq -= 8;
72 }
73 ddb5074_led_hex(9);
74 t = ddb_in32(offset);
75 ddb5074_led_hex(0xa);
76 t |= 8 << (nile4_irq * 4);
77 ddb_out32(offset, t);
78 ddb5074_led_hex(0xb);
79}
80
81void nile4_disable_irq(unsigned int nile4_irq)
82{
83 u32 offset, t;
84
85 nile4_irq-=irq_base;
86
87 offset = DDB_INTCTRL;
88 if (nile4_irq >= 8) {
89 offset += 4;
90 nile4_irq -= 8;
91 }
92 t = ddb_in32(offset);
93 t &= ~(8 << (nile4_irq * 4));
94 ddb_out32(offset, t);
95}
96
97void nile4_disable_irq_all(void)
98{
99 ddb_out32(DDB_INTCTRL, 0);
100 ddb_out32(DDB_INTCTRL + 4, 0);
101}
102
103u16 nile4_get_irq_stat(int cpu_irq)
104{
105 return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
106}
107
108void nile4_enable_irq_output(int cpu_irq)
109{
110 u32 t;
111
112 t = ddb_in32(DDB_INTSTAT1 + 4);
113 t |= 1 << (16 + cpu_irq);
114 ddb_out32(DDB_INTSTAT1, t);
115}
116
117void nile4_disable_irq_output(int cpu_irq)
118{
119 u32 t;
120
121 t = ddb_in32(DDB_INTSTAT1 + 4);
122 t &= ~(1 << (16 + cpu_irq));
123 ddb_out32(DDB_INTSTAT1, t);
124}
125
126void nile4_set_pci_irq_polarity(int pci_irq, int high)
127{
128 u32 t;
129
130 t = ddb_in32(DDB_INTPPES);
131 if (high)
132 t &= ~(1 << (pci_irq * 2));
133 else
134 t |= 1 << (pci_irq * 2);
135 ddb_out32(DDB_INTPPES, t);
136}
137
138void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
139{
140 u32 t;
141
142 t = ddb_in32(DDB_INTPPES);
143 if (level)
144 t |= 2 << (pci_irq * 2);
145 else
146 t &= ~(2 << (pci_irq * 2));
147 ddb_out32(DDB_INTPPES, t);
148}
149
150void nile4_clear_irq(int nile4_irq)
151{
152 nile4_irq-=irq_base;
153 ddb_out32(DDB_INTCLR, 1 << nile4_irq);
154}
155
156void nile4_clear_irq_mask(u32 mask)
157{
158 ddb_out32(DDB_INTCLR, mask);
159}
160
161u8 nile4_i8259_iack(void)
162{
163 u8 irq;
164 u32 reg;
165
166 /* Set window 0 for interrupt acknowledge */
167 reg = ddb_in32(DDB_PCIINIT0);
168
169 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
170 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
171 /* restore window 0 for PCI I/O space */
172 // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
173 ddb_out32(DDB_PCIINIT0, reg);
174
175 /* i8269.c set the base vector to be 0x0 */
176 return irq ;
177}
178
179static unsigned int nile4_irq_startup(unsigned int irq) {
180
181 nile4_enable_irq(irq);
182 return 0;
183
184}
185
186static void nile4_ack_irq(unsigned int irq) {
187
188 ddb5074_led_hex(4);
189
190 nile4_clear_irq(irq);
191 ddb5074_led_hex(2);
192 nile4_disable_irq(irq);
193
194 ddb5074_led_hex(0);
195}
196
197static void nile4_irq_end(unsigned int irq) {
198
199 ddb5074_led_hex(3);
200 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
201 ddb5074_led_hex(5);
202 nile4_enable_irq(irq);
203 ddb5074_led_hex(7);
204 }
205
206 ddb5074_led_hex(1);
207}
208
209#define nile4_irq_shutdown nile4_disable_irq
210
211static hw_irq_controller nile4_irq_controller = {
212 .typename = "nile4",
213 .startup = nile4_irq_startup,
214 .shutdown = nile4_irq_shutdown,
215 .enable = nile4_enable_irq,
216 .disable = nile4_disable_irq,
217 .ack = nile4_ack_irq,
218 .end = nile4_irq_end,
219};
220
221void nile4_irq_setup(u32 base) {
222
223 int i;
224
225 irq_base=base;
226
227 /* Map all interrupts to CPU int #0 */
228 nile4_map_irq_all(0);
229
230 /* PCI INTA#-E# must be level triggered */
231 nile4_set_pci_irq_level_or_edge(0, 1);
232 nile4_set_pci_irq_level_or_edge(1, 1);
233 nile4_set_pci_irq_level_or_edge(2, 1);
234 nile4_set_pci_irq_level_or_edge(3, 1);
235 nile4_set_pci_irq_level_or_edge(4, 1);
236
237 /* PCI INTA#-D# must be active low, INTE# must be active high */
238 nile4_set_pci_irq_polarity(0, 0);
239 nile4_set_pci_irq_polarity(1, 0);
240 nile4_set_pci_irq_polarity(2, 0);
241 nile4_set_pci_irq_polarity(3, 0);
242 nile4_set_pci_irq_polarity(4, 1);
243
244
245 for (i = 0; i < 16; i++) {
246 nile4_clear_irq(i);
247 nile4_disable_irq(i);
248 }
249
250 /* Enable CPU int #0 */
251 nile4_enable_irq_output(0);
252
253 for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
254 irq_desc[i].status = IRQ_DISABLED;
255 irq_desc[i].action = NULL;
256 irq_desc[i].depth = 1;
257 irq_desc[i].handler = &nile4_irq_controller;
258 }
259}
260
261#if defined(CONFIG_RUNTIME_DEBUG)
262void nile4_dump_irq_status(void)
263{
264 printk(KERN_DEBUG "
265 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
266 (void *) ddb_in32(DDB_CPUSTAT));
267 printk(KERN_DEBUG "
268 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
269 (void *) ddb_in32(DDB_INTCTRL));
270 printk(KERN_DEBUG
271 "INTSTAT0 = %p:%p\n",
272 (void *) ddb_in32(DDB_INTSTAT0 + 4),
273 (void *) ddb_in32(DDB_INTSTAT0));
274 printk(KERN_DEBUG
275 "INTSTAT1 = %p:%p\n",
276 (void *) ddb_in32(DDB_INTSTAT1 + 4),
277 (void *) ddb_in32(DDB_INTSTAT1));
278 printk(KERN_DEBUG
279 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
280 (void *) ddb_in32(DDB_INTCLR));
281 printk(KERN_DEBUG
282 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
283 (void *) ddb_in32(DDB_INTPPES));
284}
285
286#endif
diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c
deleted file mode 100644
index 91456b068c2e..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/setup.c
+++ /dev/null
@@ -1,234 +0,0 @@
1/*
2 * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/ide.h>
15#include <linux/ioport.h>
16#include <linux/irq.h>
17#include <linux/pm.h>
18
19#include <asm/addrspace.h>
20#include <asm/bcache.h>
21#include <asm/irq.h>
22#include <asm/reboot.h>
23#include <asm/gdb-stub.h>
24#include <asm/time.h>
25#include <asm/nile4.h>
26#include <asm/ddb5xxx/ddb5074.h>
27#include <asm/ddb5xxx/ddb5xxx.h>
28
29static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
30
31static void ddb_machine_restart(char *command)
32{
33 u32 t;
34
35 /* PCI cold reset */
36 t = nile4_in32(NILE4_PCICTRL + 4);
37 t |= 0x40000000;
38 nile4_out32(NILE4_PCICTRL + 4, t);
39 /* CPU cold reset */
40 t = nile4_in32(NILE4_CPUSTAT);
41 t |= 1;
42 nile4_out32(NILE4_CPUSTAT, t);
43 /* Call the PROM */
44 back_to_prom();
45}
46
47static void ddb_machine_halt(void)
48{
49 printk("DDB Vrc-5074 halted.\n");
50 do {
51 } while (1);
52}
53
54static void ddb_machine_power_off(void)
55{
56 printk("DDB Vrc-5074 halted. Please turn off the power.\n");
57 do {
58 } while (1);
59}
60
61extern void rtc_ds1386_init(unsigned long base);
62
63extern void (*board_timer_setup) (struct irqaction * irq);
64
65static void __init ddb_timer_init(struct irqaction *irq)
66{
67 /* set the clock to 1 Hz */
68 nile4_out32(NILE4_T2CTRL, 1000000);
69 /* enable the General-Purpose Timer */
70 nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
71 /* reset timer */
72 nile4_out32(NILE4_T2CNTR, 0);
73 /* enable interrupt */
74 setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
75 nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
76 change_c0_status(ST0_IM,
77 IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
78
79}
80
81static void __init ddb_time_init(void)
82{
83 /* we have ds1396 RTC chip */
84 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
85}
86
87
88
89void __init plat_setup(void)
90{
91 set_io_port_base(NILE4_PCI_IO_BASE);
92 isa_slot_offset = NILE4_PCI_MEM_BASE;
93 board_timer_setup = ddb_timer_init;
94 board_time_init = ddb_time_init;
95
96
97 _machine_restart = ddb_machine_restart;
98 _machine_halt = ddb_machine_halt;
99 pm_power_off = ddb_machine_power_off;
100
101 ddb_out32(DDB_BAR0, 0);
102
103 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10);
104 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
105
106 /* Reboot on panic */
107 panic_timeout = 180;
108}
109
110#define USE_NILE4_SERIAL 0
111
112#if USE_NILE4_SERIAL
113#define ns16550_in(reg) nile4_in8((reg)*8)
114#define ns16550_out(reg, val) nile4_out8((reg)*8, (val))
115#else
116#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8)
117static inline u8 ns16550_in(u32 reg)
118{
119 return *(volatile u8 *) (NS16550_BASE + reg);
120}
121
122static inline void ns16550_out(u32 reg, u8 val)
123{
124 *(volatile u8 *) (NS16550_BASE + reg) = val;
125}
126#endif
127
128#define NS16550_RBR 0
129#define NS16550_THR 0
130#define NS16550_DLL 0
131#define NS16550_IER 1
132#define NS16550_DLM 1
133#define NS16550_FCR 2
134#define NS16550_IIR 2
135#define NS16550_LCR 3
136#define NS16550_MCR 4
137#define NS16550_LSR 5
138#define NS16550_MSR 6
139#define NS16550_SCR 7
140
141#define NS16550_LSR_DR 0x01 /* Data ready */
142#define NS16550_LSR_OE 0x02 /* Overrun */
143#define NS16550_LSR_PE 0x04 /* Parity error */
144#define NS16550_LSR_FE 0x08 /* Framing error */
145#define NS16550_LSR_BI 0x10 /* Break */
146#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */
147#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */
148#define NS16550_LSR_ERR 0x80 /* Error */
149
150
151void _serinit(void)
152{
153#if USE_NILE4_SERIAL
154 ns16550_out(NS16550_LCR, 0x80);
155 ns16550_out(NS16550_DLM, 0x00);
156 ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */
157 ns16550_out(NS16550_LCR, 0x00);
158 ns16550_out(NS16550_LCR, 0x03);
159 ns16550_out(NS16550_FCR, 0x47);
160#else
161 /* done by PMON */
162#endif
163}
164
165void _putc(char c)
166{
167 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
168 ns16550_out(NS16550_THR, c);
169 if (c == '\n') {
170 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
171 ns16550_out(NS16550_THR, '\r');
172 }
173}
174
175void _puts(const char *s)
176{
177 char c;
178 while ((c = *s++))
179 _putc(c);
180}
181
182char _getc(void)
183{
184 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
185 return ns16550_in(NS16550_RBR);
186}
187
188int _testc(void)
189{
190 return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
191}
192
193
194/*
195 * Hexadecimal 7-segment LED
196 */
197void ddb5074_led_hex(int hex)
198{
199 outb(hex, 0x80);
200}
201
202
203/*
204 * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
205 */
206struct pci_dev *pci_pmu = NULL;
207
208void ddb5074_led_d2(int on)
209{
210 u8 t;
211
212 if (pci_pmu) {
213 pci_read_config_byte(pci_pmu, 0x7e, &t);
214 if (on)
215 t &= 0x7f;
216 else
217 t |= 0x80;
218 pci_write_config_byte(pci_pmu, 0x7e, t);
219 }
220}
221
222void ddb5074_led_d3(int on)
223{
224 u8 t;
225
226 if (pci_pmu) {
227 pci_read_config_byte(pci_pmu, 0x7e, &t);
228 if (on)
229 t &= 0xbf;
230 else
231 t |= 0x40;
232 pci_write_config_byte(pci_pmu, 0x7e, t);
233 }
234}
diff --git a/arch/mips/ddb5xxx/ddb5476/Makefile b/arch/mips/ddb5xxx/ddb5476/Makefile
deleted file mode 100644
index ab0312cb47b4..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines
3# under Linux.
4#
5
6obj-y += setup.o irq.o nile4_pic.o vrc5476_irq.o
7obj-$(CONFIG_KGDB) += dbg_io.o
8
9EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5476/dbg_io.c b/arch/mips/ddb5xxx/ddb5476/dbg_io.c
deleted file mode 100644
index f2296a999953..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/dbg_io.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * kgdb io functions for DDB5476. We use the second serial port.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* ======================= CONFIG ======================== */
15
16/* [jsun] we use the second serial port for kdb */
17#define BASE 0xa60002f8
18#define MAX_BAUD 115200
19
20/* distance in bytes between two serial registers */
21#define REG_OFFSET 1
22
23/*
24 * 0 - kgdb does serial init
25 * 1 - kgdb skip serial init
26 */
27static int remoteDebugInitialized = 0;
28
29/*
30 * the default baud rate *if* kgdb does serial init
31 */
32#define BAUD_DEFAULT UART16550_BAUD_38400
33
34/* ======================= END OF CONFIG ======================== */
35
36typedef unsigned char uint8;
37typedef unsigned int uint32;
38
39#define UART16550_BAUD_2400 2400
40#define UART16550_BAUD_4800 4800
41#define UART16550_BAUD_9600 9600
42#define UART16550_BAUD_19200 19200
43#define UART16550_BAUD_38400 38400
44#define UART16550_BAUD_57600 57600
45#define UART16550_BAUD_115200 115200
46
47#define UART16550_PARITY_NONE 0
48#define UART16550_PARITY_ODD 0x08
49#define UART16550_PARITY_EVEN 0x18
50#define UART16550_PARITY_MARK 0x28
51#define UART16550_PARITY_SPACE 0x38
52
53#define UART16550_DATA_5BIT 0x0
54#define UART16550_DATA_6BIT 0x1
55#define UART16550_DATA_7BIT 0x2
56#define UART16550_DATA_8BIT 0x3
57
58#define UART16550_STOP_1BIT 0x0
59#define UART16550_STOP_2BIT 0x4
60
61/* register offset */
62#define OFS_RCV_BUFFER 0
63#define OFS_TRANS_HOLD 0
64#define OFS_SEND_BUFFER 0
65#define OFS_INTR_ENABLE (1*REG_OFFSET)
66#define OFS_INTR_ID (2*REG_OFFSET)
67#define OFS_DATA_FORMAT (3*REG_OFFSET)
68#define OFS_LINE_CONTROL (3*REG_OFFSET)
69#define OFS_MODEM_CONTROL (4*REG_OFFSET)
70#define OFS_RS232_OUTPUT (4*REG_OFFSET)
71#define OFS_LINE_STATUS (5*REG_OFFSET)
72#define OFS_MODEM_STATUS (6*REG_OFFSET)
73#define OFS_RS232_INPUT (6*REG_OFFSET)
74#define OFS_SCRATCH_PAD (7*REG_OFFSET)
75
76#define OFS_DIVISOR_LSB (0*REG_OFFSET)
77#define OFS_DIVISOR_MSB (1*REG_OFFSET)
78
79
80/* memory-mapped read/write of the port */
81#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
82#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
83
84void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
85{
86 /* disable interrupts */
87 UART16550_WRITE(OFS_INTR_ENABLE, 0);
88
89 /* set up baud rate */
90 {
91 uint32 divisor;
92
93 /* set DIAB bit */
94 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
95
96 /* set divisor */
97 divisor = MAX_BAUD / baud;
98 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
99 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
100
101 /* clear DIAB bit */
102 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
103 }
104
105 /* set data format */
106 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
107}
108
109
110uint8 getDebugChar(void)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(BAUD_DEFAULT,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
120 return UART16550_READ(OFS_RCV_BUFFER);
121}
122
123
124int putDebugChar(uint8 byte)
125{
126 if (!remoteDebugInitialized) {
127 remoteDebugInitialized = 1;
128 debugInit(BAUD_DEFAULT,
129 UART16550_DATA_8BIT,
130 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
131 }
132
133 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
134 UART16550_WRITE(OFS_SEND_BUFFER, byte);
135 return 1;
136}
diff --git a/arch/mips/ddb5xxx/ddb5476/irq.c b/arch/mips/ddb5xxx/ddb5476/irq.c
deleted file mode 100644
index 7583a1f30711..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/irq.c
+++ /dev/null
@@ -1,165 +0,0 @@
1/*
2 * arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 *
7 * Re-write the whole thing to use new irq.c file.
8 * Copyright (C) 2001 MontaVista Software Inc.
9 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16
17#include <asm/i8259.h>
18#include <asm/io.h>
19#include <asm/ptrace.h>
20
21#include <asm/ddb5xxx/ddb5xxx.h>
22
23#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
24#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
25#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
26
27#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
28#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
29#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
30
31#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
32#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
33
34#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
35#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
36
37#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
38#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
39
40static void m1543_irq_setup(void)
41{
42 /*
43 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
44 * the possible IO sources in the M1543 are in use by us. We will
45 * use the following mapping:
46 *
47 * IRQ1 - keyboard (default set by M1543)
48 * IRQ3 - reserved for UART B (default set by M1543) (note that
49 * the schematics for the DDB Vrc-5476 board seem to
50 * indicate that IRQ3 is connected to the DS1386
51 * watchdog timer interrupt output so we might have
52 * a conflict)
53 * IRQ4 - reserved for UART A (default set by M1543)
54 * IRQ5 - parallel (default set by M1543)
55 * IRQ8 - DS1386 time of day (RTC) interrupt
56 * IRQ9 - USB (hardwired in ddb_setup)
57 * IRQ10 - PMU (hardwired in ddb_setup)
58 * IRQ12 - mouse
59 * IRQ14,15 - IDE controller (need to be confirmed, jsun)
60 */
61
62 /*
63 * Assing mouse interrupt to IRQ12
64 */
65
66 /* Enter configuration mode */
67 outb(0x51, M1543_PNP_CONFIG);
68 outb(0x23, M1543_PNP_CONFIG);
69
70 /* Select logical device 7 (Keyboard) */
71 outb(0x07, M1543_PNP_INDEX);
72 outb(0x07, M1543_PNP_DATA);
73
74 /* Select IRQ12 */
75 outb(0x72, M1543_PNP_INDEX);
76 outb(0x0c, M1543_PNP_DATA);
77
78 /* Leave configration mode */
79 outb(0xbb, M1543_PNP_CONFIG);
80}
81
82static void nile4_irq_setup(void)
83{
84 int i;
85
86 /* Map all interrupts to CPU int #0 (IP2) */
87 nile4_map_irq_all(0);
88
89 /* PCI INTA#-E# must be level triggered */
90 nile4_set_pci_irq_level_or_edge(0, 1);
91 nile4_set_pci_irq_level_or_edge(1, 1);
92 nile4_set_pci_irq_level_or_edge(2, 1);
93 nile4_set_pci_irq_level_or_edge(3, 1);
94
95 /* PCI INTA#, B#, D# must be active low, INTC# must be active high */
96 nile4_set_pci_irq_polarity(0, 0);
97 nile4_set_pci_irq_polarity(1, 0);
98 nile4_set_pci_irq_polarity(2, 1);
99 nile4_set_pci_irq_polarity(3, 0);
100
101 for (i = 0; i < 16; i++)
102 nile4_clear_irq(i);
103
104 /* Enable CPU int #0 */
105 nile4_enable_irq_output(0);
106
107 /* memory resource acquire in ddb_setup */
108}
109
110static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
111static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL };
112
113extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
114extern void mips_cpu_irq_init(u32 irq_base);
115extern void vrc5476_irq_init(u32 irq_base);
116
117extern void vrc5476_irq_dispatch(struct pt_regs *regs);
118
119asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
120{
121 unsigned int pending = read_c0_cause() & read_c0_status();
122
123 if (pending & STATUSF_IP7)
124 do_IRQ(CPU_IRQ_BASE + 7, regs);
125 else if (pending & STATUSF_IP2)
126 vrc5476_irq_dispatch(regs);
127 else if (pending & STATUSF_IP3)
128 do_IRQ(CPU_IRQ_BASE + 3, regs);
129 else if (pending & STATUSF_IP4)
130 do_IRQ(CPU_IRQ_BASE + 4, regs);
131 else if (pending & STATUSF_IP5)
132 do_IRQ(CPU_IRQ_BASE + 5, regs);
133 else if (pending & STATUSF_IP6)
134 do_IRQ(CPU_IRQ_BASE + 6, regs);
135 else if (pending & STATUSF_IP0)
136 do_IRQ(CPU_IRQ_BASE, regs);
137 else if (pending & STATUSF_IP1)
138 do_IRQ(CPU_IRQ_BASE + 1, regs);
139
140 vrc5476_irq_dispatch(regs);
141}
142
143void __init arch_init_irq(void)
144{
145 /* hardware initialization */
146 nile4_irq_setup();
147 m1543_irq_setup();
148
149 /* controller setup */
150 init_i8259_irqs();
151 vrc5476_irq_init(VRC5476_IRQ_BASE);
152 mips_cpu_irq_init(CPU_IRQ_BASE);
153
154 /* setup cascade interrupts */
155 setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
156 setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
157
158 /* setup error interrupts for debugging */
159 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
160 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
161 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
162 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
163 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
164 setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
165}
diff --git a/arch/mips/ddb5xxx/ddb5476/nile4_pic.c b/arch/mips/ddb5xxx/ddb5476/nile4_pic.c
deleted file mode 100644
index e930cee7944f..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/nile4_pic.c
+++ /dev/null
@@ -1,190 +0,0 @@
1/*
2 * arch/mips/ddb5476/nile4.c --
3 * low-level PIC code for NEC Vrc-5476 (Nile 4)
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15
16#include <asm/addrspace.h>
17
18#include <asm/ddb5xxx/ddb5xxx.h>
19
20
21/*
22 * Interrupt Programming
23 */
24void nile4_map_irq(int nile4_irq, int cpu_irq)
25{
26 u32 offset, t;
27
28 offset = DDB_INTCTRL;
29 if (nile4_irq >= 8) {
30 offset += 4;
31 nile4_irq -= 8;
32 }
33 t = ddb_in32(offset);
34 t &= ~(7 << (nile4_irq * 4));
35 t |= cpu_irq << (nile4_irq * 4);
36 ddb_out32(offset, t);
37}
38
39void nile4_map_irq_all(int cpu_irq)
40{
41 u32 all, t;
42
43 all = cpu_irq;
44 all |= all << 4;
45 all |= all << 8;
46 all |= all << 16;
47 t = ddb_in32(DDB_INTCTRL);
48 t &= 0x88888888;
49 t |= all;
50 ddb_out32(DDB_INTCTRL, t);
51 t = ddb_in32(DDB_INTCTRL + 4);
52 t &= 0x88888888;
53 t |= all;
54 ddb_out32(DDB_INTCTRL + 4, t);
55}
56
57void nile4_enable_irq(int nile4_irq)
58{
59 u32 offset, t;
60
61 offset = DDB_INTCTRL;
62 if (nile4_irq >= 8) {
63 offset += 4;
64 nile4_irq -= 8;
65 }
66 t = ddb_in32(offset);
67 t |= 8 << (nile4_irq * 4);
68 ddb_out32(offset, t);
69}
70
71void nile4_disable_irq(int nile4_irq)
72{
73 u32 offset, t;
74
75 offset = DDB_INTCTRL;
76 if (nile4_irq >= 8) {
77 offset += 4;
78 nile4_irq -= 8;
79 }
80 t = ddb_in32(offset);
81 t &= ~(8 << (nile4_irq * 4));
82 ddb_out32(offset, t);
83}
84
85void nile4_disable_irq_all(void)
86{
87 ddb_out32(DDB_INTCTRL, 0);
88 ddb_out32(DDB_INTCTRL + 4, 0);
89}
90
91u16 nile4_get_irq_stat(int cpu_irq)
92{
93 return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
94}
95
96void nile4_enable_irq_output(int cpu_irq)
97{
98 u32 t;
99
100 t = ddb_in32(DDB_INTSTAT1 + 4);
101 t |= 1 << (16 + cpu_irq);
102 ddb_out32(DDB_INTSTAT1, t);
103}
104
105void nile4_disable_irq_output(int cpu_irq)
106{
107 u32 t;
108
109 t = ddb_in32(DDB_INTSTAT1 + 4);
110 t &= ~(1 << (16 + cpu_irq));
111 ddb_out32(DDB_INTSTAT1, t);
112}
113
114void nile4_set_pci_irq_polarity(int pci_irq, int high)
115{
116 u32 t;
117
118 t = ddb_in32(DDB_INTPPES);
119 if (high)
120 t &= ~(1 << (pci_irq * 2));
121 else
122 t |= 1 << (pci_irq * 2);
123 ddb_out32(DDB_INTPPES, t);
124}
125
126void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
127{
128 u32 t;
129
130 t = ddb_in32(DDB_INTPPES);
131 if (level)
132 t |= 2 << (pci_irq * 2);
133 else
134 t &= ~(2 << (pci_irq * 2));
135 ddb_out32(DDB_INTPPES, t);
136}
137
138void nile4_clear_irq(int nile4_irq)
139{
140 ddb_out32(DDB_INTCLR, 1 << nile4_irq);
141}
142
143void nile4_clear_irq_mask(u32 mask)
144{
145 ddb_out32(DDB_INTCLR, mask);
146}
147
148u8 nile4_i8259_iack(void)
149{
150 u8 irq;
151 u32 reg;
152
153 /* Set window 0 for interrupt acknowledge */
154 reg = ddb_in32(DDB_PCIINIT0);
155
156 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
157 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
158 /* restore window 0 for PCI I/O space */
159 // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
160 ddb_out32(DDB_PCIINIT0, reg);
161
162 /* i8269.c set the base vector to be 0x0 */
163 return irq + I8259_IRQ_BASE;
164}
165
166#if defined(CONFIG_RUNTIME_DEBUG)
167void nile4_dump_irq_status(void)
168{
169 printk(KERN_DEBUG "
170 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
171 (void *) ddb_in32(DDB_CPUSTAT));
172 printk(KERN_DEBUG "
173 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
174 (void *) ddb_in32(DDB_INTCTRL));
175 printk(KERN_DEBUG
176 "INTSTAT0 = %p:%p\n",
177 (void *) ddb_in32(DDB_INTSTAT0 + 4),
178 (void *) ddb_in32(DDB_INTSTAT0));
179 printk(KERN_DEBUG
180 "INTSTAT1 = %p:%p\n",
181 (void *) ddb_in32(DDB_INTSTAT1 + 4),
182 (void *) ddb_in32(DDB_INTSTAT1));
183 printk(KERN_DEBUG
184 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
185 (void *) ddb_in32(DDB_INTCLR));
186 printk(KERN_DEBUG
187 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
188 (void *) ddb_in32(DDB_INTPPES));
189}
190#endif
diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c
deleted file mode 100644
index c902adef5942..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/setup.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/pm.h>
15
16#include <asm/addrspace.h>
17#include <asm/bcache.h>
18#include <asm/irq.h>
19#include <asm/reboot.h>
20#include <asm/gdb-stub.h>
21#include <asm/time.h>
22#include <asm/debug.h>
23#include <asm/traps.h>
24
25#include <asm/ddb5xxx/ddb5xxx.h>
26
27// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
28
29#ifdef USE_CPU_COUNTER_TIMER
30
31#define CPU_COUNTER_FREQUENCY 83000000
32#else
33/* otherwise we use general purpose timer */
34#define TIMER_FREQUENCY 83000000
35#define TIMER_BASE DDB_T2CTRL
36#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
37#endif
38
39static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
40
41static void ddb_machine_restart(char *command)
42{
43 u32 t;
44
45 /* PCI cold reset */
46 t = ddb_in32(DDB_PCICTRL + 4);
47 t |= 0x40000000;
48 ddb_out32(DDB_PCICTRL + 4, t);
49 /* CPU cold reset */
50 t = ddb_in32(DDB_CPUSTAT);
51 t |= 1;
52 ddb_out32(DDB_CPUSTAT, t);
53 /* Call the PROM */
54 back_to_prom();
55}
56
57static void ddb_machine_halt(void)
58{
59 printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
60 while (1);
61}
62
63static void ddb_machine_power_off(void)
64{
65 printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
66 while (1);
67}
68
69extern void rtc_ds1386_init(unsigned long base);
70
71static void __init ddb_time_init(void)
72{
73#if defined(USE_CPU_COUNTER_TIMER)
74 mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
75#endif
76
77 /* we have ds1396 RTC chip */
78 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
79}
80
81
82extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
83static void __init ddb_timer_setup(struct irqaction *irq)
84{
85#if defined(USE_CPU_COUNTER_TIMER)
86
87 unsigned int count;
88
89 /* we are using the cpu counter for timer interrupts */
90 setup_irq(CPU_IRQ_BASE + 7, irq);
91
92 /* to generate the first timer interrupt */
93 count = read_c0_count();
94 write_c0_compare(count + 1000);
95
96#else
97
98 ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
99 ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */
100 setup_irq(TIMER_IRQ, irq);
101#endif
102}
103
104static struct {
105 struct resource dma1;
106 struct resource timer;
107 struct resource rtc;
108 struct resource dma_page_reg;
109 struct resource dma2;
110} ddb5476_ioport = {
111 {
112 "dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
113 "timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
114 "rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
115 "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
116 "dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
117};
118
119static struct {
120 struct resource nile4;
121} ddb5476_iomem = {
122 { "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
123};
124
125
126static void ddb5476_board_init(void);
127
128void __init plat_setup(void)
129{
130 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
131
132 board_time_init = ddb_time_init;
133 board_timer_setup = ddb_timer_setup;
134
135 _machine_restart = ddb_machine_restart;
136 _machine_halt = ddb_machine_halt;
137 pm_power_off = ddb_machine_power_off;
138
139 /* request io port/mem resources */
140 if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
141 request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
142 request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
143 request_resource(&ioport_resource,
144 &ddb5476_ioport.dma_page_reg)
145 || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
146 || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
147 printk
148 ("ddb_setup - requesting oo port resources failed.\n");
149 for (;;);
150 }
151
152 /* Reboot on panic */
153 panic_timeout = 180;
154
155 /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
156 /* *(long*)0xbfa00218 = 0x8; */
157
158 /* board initialization stuff */
159 ddb5476_board_init();
160}
161
162/*
163 * We don't trust bios. We essentially does hardware re-initialization
164 * as complete as possible, as far as we know we can safely do.
165 */
166static void ddb5476_board_init(void)
167{
168 /* ----------- setup PDARs ------------ */
169 /* check SDRAM0, whether we are on MEM bus does not matter */
170 db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
171 ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
172
173 /* SDRAM1 should be turned off. What is this for anyway ? */
174 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
175
176 /* flash 1&2, DDB status, DDB control */
177 ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
178 ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
179 ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
180 ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
181
182 /* shut off other pdar so they don't accidentally get into the way */
183 ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
184 ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
185 ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
186
187 /* verify VRC5477 base addr */
188 /* don't care about some details */
189 db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
190 ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
191
192 /* verify BOOT ROM addr */
193 /* don't care about some details */
194 db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
195 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
196
197 /* setup PCI windows - window1 for MEM/config, window0 for IO */
198 ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
199 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
200
201 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
202 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
203
204 /* ----------- setup PDARs ------------ */
205 /* this is problematic - it will reset Aladin which cause we loose
206 * serial port, and we don't know how to set up Aladin chip again.
207 */
208 // ddb_pci_reset_bus();
209
210 ddb_out32(DDB_BAR0, 0x00000008);
211
212 ddb_out32(DDB_BARC, 0xffffffff);
213 ddb_out32(DDB_BARB, 0xffffffff);
214 ddb_out32(DDB_BAR1, 0xffffffff);
215 ddb_out32(DDB_BAR2, 0xffffffff);
216 ddb_out32(DDB_BAR3, 0xffffffff);
217 ddb_out32(DDB_BAR4, 0xffffffff);
218 ddb_out32(DDB_BAR5, 0xffffffff);
219 ddb_out32(DDB_BAR6, 0xffffffff);
220 ddb_out32(DDB_BAR7, 0xffffffff);
221 ddb_out32(DDB_BAR8, 0xffffffff);
222
223 /* ----------- switch PCI1 to PCI CONFIG space ------------ */
224 ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
225 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
226
227 /* ----- M1543 PCI setup ------ */
228
229 /* we know M1543 PCI-ISA controller is at addr:18 */
230 /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
231 *(volatile unsigned char *) 0xa8040072 &= 0xf0;
232 *(volatile unsigned char *) 0xa8040072 |= 0xa;
233
234 /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
235 * no IOCHRDY signal, (bit 7 - 1)
236 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
237 * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
238 */
239 *(unsigned char *) 0xa8040074 = 0xd1;
240
241 /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
242 * SCI routing to IRQ 13 disabled (bit 7 - 1)
243 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
244 */
245 *(unsigned char *) 0xa8040076 = 0x83;
246
247 /* setup IDE controller
248 * enable IDE controller (bit 6 - 1)
249 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
250 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
251 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
252 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
253 */
254 // *(unsigned char*)0xa8040058 = 0x71;
255 // *(unsigned char*)0xa8040058 = 0x79;
256 // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state
257 *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state
258
259#if 0
260 /* this is not necessary if M5229 does not use SIRQ */
261 *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14
262 *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14
263#endif
264
265 /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
266 /* M5229 IDSEL is addr:24; see above setting */
267 *(unsigned char *) 0xa9000050 |= 0x1;
268
269 /* enable bus master (bit 2) and IO decoding (bit 0) */
270 *(unsigned char *) 0xa9000004 |= 0x5;
271
272 /* enable native, copied from arch/ppc/k2boot/head.S */
273 /* TODO - need volatile, need to be portable */
274 *(unsigned char *) 0xa9000009 = 0xff;
275
276 /* ----- end of M1543 PCI setup ------ */
277
278 /* ----- reset on-board ether chip ------ */
279 *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */
280 *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */
281
282 /* send reset command */
283 *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */
284
285 /* disable ether chip */
286 *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */
287
288 /* put it into sleep */
289 *((volatile u32 *) 0xa8020040) = 0x80000000;
290
291 /* ----- end of reset on-board ether chip ------ */
292
293 /* ----------- switch PCI1 back to PCI MEM space ------------ */
294 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
295 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
296}
diff --git a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
deleted file mode 100644
index a3c5e7b18018..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * The irq controller for vrc5476.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/types.h>
17#include <linux/ptrace.h>
18
19#include <asm/system.h>
20
21#include <asm/ddb5xxx/ddb5xxx.h>
22
23static int irq_base;
24
25static void vrc5476_irq_enable(uint irq)
26{
27 nile4_enable_irq(irq - irq_base);
28}
29
30static void vrc5476_irq_disable(uint irq)
31{
32 nile4_disable_irq(irq - irq_base);
33}
34
35static unsigned int vrc5476_irq_startup(uint irq)
36{
37 nile4_enable_irq(irq - irq_base);
38 return 0;
39}
40
41#define vrc5476_irq_shutdown vrc5476_irq_disable
42
43static void vrc5476_irq_ack(uint irq)
44{
45 nile4_clear_irq(irq - irq_base);
46 nile4_disable_irq(irq - irq_base);
47}
48
49static void vrc5476_irq_end(uint irq)
50{
51 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
52 vrc5476_irq_enable(irq);
53}
54
55static hw_irq_controller vrc5476_irq_controller = {
56 .typename = "vrc5476",
57 .startup = vrc5476_irq_startup,
58 .shutdown = vrc5476_irq_shutdown,
59 .enable = vrc5476_irq_enable,
60 .disable = vrc5476_irq_disable,
61 .ack = vrc5476_irq_ack,
62 .end = vrc5476_irq_end
63};
64
65void __init
66vrc5476_irq_init(u32 base)
67{
68 u32 i;
69
70 irq_base = base;
71 for (i= base; i< base + NUM_VRC5476_IRQ; i++) {
72 irq_desc[i].status = IRQ_DISABLED;
73 irq_desc[i].action = NULL;
74 irq_desc[i].depth = 1;
75 irq_desc[i].handler = &vrc5476_irq_controller;
76 }
77}
78
79
80void
81vrc5476_irq_dispatch(struct pt_regs *regs)
82{
83 u32 mask;
84 int nile4_irq;
85
86 mask = nile4_get_irq_stat(0);
87
88 /* quick check for possible time interrupt */
89 if (mask & (1 << VRC5476_IRQ_GPT)) {
90 do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs);
91 return;
92 }
93
94 /* check for i8259 interrupts */
95 if (mask & (1 << VRC5476_I8259_CASCADE)) {
96 int i8259_irq = nile4_i8259_iack();
97 do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
98 return;
99 }
100
101 /* regular nile4 interrupts (we should not really have any */
102 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) {
103 if (mask & 1) {
104 do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs);
105 return;
106 }
107 }
108 spurious_interrupt(regs);
109}
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
index 2f566034cc44..93167ecdb424 100644
--- a/arch/mips/ddb5xxx/ddb5477/setup.c
+++ b/arch/mips/ddb5xxx/ddb5477/setup.c
@@ -171,7 +171,7 @@ static void ddb5477_board_init(void);
171extern struct pci_controller ddb5477_ext_controller; 171extern struct pci_controller ddb5477_ext_controller;
172extern struct pci_controller ddb5477_io_controller; 172extern struct pci_controller ddb5477_io_controller;
173 173
174void __init plat_setup(void) 174void __init plat_mem_setup(void)
175{ 175{
176 /* initialize board - we don't trust the loader */ 176 /* initialize board - we don't trust the loader */
177 ddb5477_board_init(); 177 ddb5477_board_init();
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 11:11:45 -0500