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-rw-r--r--arch/mips/ddb5xxx/ddb5477/Makefile10
-rw-r--r--arch/mips/ddb5xxx/ddb5477/debug.c160
-rw-r--r--arch/mips/ddb5xxx/ddb5477/int-handler.S75
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c199
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c168
-rw-r--r--arch/mips/ddb5xxx/ddb5477/kgdb_io.c136
-rw-r--r--arch/mips/ddb5xxx/ddb5477/lcd44780.c92
-rw-r--r--arch/mips/ddb5xxx/ddb5477/lcd44780.h15
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c405
9 files changed, 1260 insertions, 0 deletions
diff --git a/arch/mips/ddb5xxx/ddb5477/Makefile b/arch/mips/ddb5xxx/ddb5477/Makefile
new file mode 100644
index 000000000000..b79b43c9f93b
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/Makefile
@@ -0,0 +1,10 @@
1#
2# Makefile for NEC DDB-Vrc5477 board
3#
4
5obj-y += int-handler.o irq.o irq_5477.o setup.o lcd44780.o
6
7obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
8obj-$(CONFIG_KGDB) += kgdb_io.o
9
10EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5477/debug.c b/arch/mips/ddb5xxx/ddb5477/debug.c
new file mode 100644
index 000000000000..68919d5f8ffd
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/debug.c
@@ -0,0 +1,160 @@
1/***********************************************************************
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * arch/mips/ddb5xxx/ddb5477/debug.c
7 * vrc5477 specific debug routines.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 ***********************************************************************
15 */
16
17#include <linux/kernel.h>
18
19#include <asm/mipsregs.h>
20#include <asm/ddb5xxx/ddb5xxx.h>
21
22typedef struct {
23 const char *regname;
24 unsigned regaddr;
25} Register;
26
27void jsun_show_regs(char *name, Register *regs)
28{
29 int i;
30
31 printk("\nshow regs: %s\n", name);
32 for(i=0;regs[i].regname!= NULL; i++) {
33 printk("%-16s= %08x\t\t(@%08x)\n",
34 regs[i].regname,
35 *(unsigned *)(regs[i].regaddr),
36 regs[i].regaddr);
37 }
38}
39
40static Register int_regs[] = {
41 {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0},
42 {"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1},
43 {"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2},
44 {"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3},
45 {"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT},
46 {"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT},
47 {"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT},
48 {"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT},
49 {"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT},
50 {"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT},
51 {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0},
52 {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1},
53 {NULL, 0x0}
54};
55
56void vrc5477_show_int_regs()
57{
58 jsun_show_regs("interrupt registers", int_regs);
59 printk("CPU CAUSE = %08x\n", read_c0_cause());
60 printk("CPU STATUS = %08x\n", read_c0_status());
61}
62static Register pdar_regs[] = {
63 {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
64 {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
65 {"DDB_LCS0", DDB_BASE + DDB_LCS0},
66 {"DDB_LCS1", DDB_BASE + DDB_LCS1},
67 {"DDB_LCS2", DDB_BASE + DDB_LCS2},
68 {"DDB_INTCS", DDB_BASE + DDB_INTCS},
69 {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
70 {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
71 {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
72 {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
73 {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
74 {NULL, 0x0}
75};
76void vrc5477_show_pdar_regs(void)
77{
78 jsun_show_regs("PDAR regs", pdar_regs);
79}
80
81static Register bar_regs[] = {
82 {"DDB_BARC0", DDB_BASE + DDB_BARC0},
83 {"DDB_BARM010", DDB_BASE + DDB_BARM010},
84 {"DDB_BARM230", DDB_BASE + DDB_BARM230},
85 {"DDB_BAR00", DDB_BASE + DDB_BAR00},
86 {"DDB_BAR10", DDB_BASE + DDB_BAR10},
87 {"DDB_BAR20", DDB_BASE + DDB_BAR20},
88 {"DDB_BAR30", DDB_BASE + DDB_BAR30},
89 {"DDB_BAR40", DDB_BASE + DDB_BAR40},
90 {"DDB_BAR50", DDB_BASE + DDB_BAR50},
91 {"DDB_BARB0", DDB_BASE + DDB_BARB0},
92 {"DDB_BARC1", DDB_BASE + DDB_BARC1},
93 {"DDB_BARM011", DDB_BASE + DDB_BARM011},
94 {"DDB_BARM231", DDB_BASE + DDB_BARM231},
95 {"DDB_BAR01", DDB_BASE + DDB_BAR01},
96 {"DDB_BAR11", DDB_BASE + DDB_BAR11},
97 {"DDB_BAR21", DDB_BASE + DDB_BAR21},
98 {"DDB_BAR31", DDB_BASE + DDB_BAR31},
99 {"DDB_BAR41", DDB_BASE + DDB_BAR41},
100 {"DDB_BAR51", DDB_BASE + DDB_BAR51},
101 {"DDB_BARB1", DDB_BASE + DDB_BARB1},
102 {NULL, 0x0}
103};
104void vrc5477_show_bar_regs(void)
105{
106 jsun_show_regs("BAR regs", bar_regs);
107}
108
109static Register pci_regs[] = {
110 {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
111 {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
112 {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00},
113 {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10},
114 {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L},
115 {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H},
116 {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L},
117 {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H},
118 {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0},
119 {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0},
120 {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
121 {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
122 {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01},
123 {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11},
124 {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L},
125 {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H},
126 {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L},
127 {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H},
128 {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1},
129 {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1},
130 {NULL, 0x0}
131};
132void vrc5477_show_pci_regs(void)
133{
134 jsun_show_regs("PCI regs", pci_regs);
135}
136
137static Register lb_regs[] = {
138 {"DDB_LCNFG", DDB_BASE + DDB_LCNFG},
139 {"DDB_LCST0", DDB_BASE + DDB_LCST0},
140 {"DDB_LCST1", DDB_BASE + DDB_LCST1},
141 {"DDB_LCST2", DDB_BASE + DDB_LCST2},
142 {"DDB_ERRADR", DDB_BASE + DDB_ERRADR},
143 {"DDB_ERRCS", DDB_BASE + DDB_ERRCS},
144 {"DDB_BTM", DDB_BASE + DDB_BTM},
145 {"DDB_BCST", DDB_BASE + DDB_BCST},
146 {NULL, 0x0}
147};
148void vrc5477_show_lb_regs(void)
149{
150 jsun_show_regs("Local Bus regs", lb_regs);
151}
152
153void vrc5477_show_all_regs(void)
154{
155 vrc5477_show_pdar_regs();
156 vrc5477_show_pci_regs();
157 vrc5477_show_bar_regs();
158 vrc5477_show_int_regs();
159 vrc5477_show_lb_regs();
160}
diff --git a/arch/mips/ddb5xxx/ddb5477/int-handler.S b/arch/mips/ddb5xxx/ddb5477/int-handler.S
new file mode 100644
index 000000000000..a2502a14400e
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/int-handler.S
@@ -0,0 +1,75 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * First-level interrupt dispatcher for ddb5477
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <asm/asm.h>
13#include <asm/mipsregs.h>
14#include <asm/addrspace.h>
15#include <asm/regdef.h>
16#include <asm/stackframe.h>
17#include <asm/ddb5xxx/ddb5477.h>
18
19/*
20 * first level interrupt dispatcher for ocelot board -
21 * We check for the timer first, then check PCI ints A and D.
22 * Then check for serial IRQ and fall through.
23 */
24 .align 5
25 NESTED(ddb5477_handle_int, PT_SIZE, sp)
26 SAVE_ALL
27 CLI
28 .set at
29 .set noreorder
30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS
32
33 and t0, t2
34
35 andi t1, t0, STATUSF_IP7 /* cpu timer */
36 bnez t1, ll_cputimer_irq
37 andi t1, t0, (STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 )
38 bnez t1, ll_vrc5477_irq
39 andi t1, t0, STATUSF_IP0 /* software int 0 */
40 bnez t1, ll_cpu_ip0
41 andi t1, t0, STATUSF_IP1 /* software int 1 */
42 bnez t1, ll_cpu_ip1
43 nop
44 .set reorder
45
46 /* wrong alarm or masked ... */
47 j spurious_interrupt
48 nop
49 END(ddb5477_handle_int)
50
51 .align 5
52
53ll_vrc5477_irq:
54 move a0, sp
55 jal vrc5477_irq_dispatch
56 j ret_from_irq
57
58ll_cputimer_irq:
59 li a0, CPU_IRQ_BASE + 7
60 move a1, sp
61 jal do_IRQ
62 j ret_from_irq
63
64
65ll_cpu_ip0:
66 li a0, CPU_IRQ_BASE + 0
67 move a1, sp
68 jal do_IRQ
69 j ret_from_irq
70
71ll_cpu_ip1:
72 li a0, CPU_IRQ_BASE + 1
73 move a1, sp
74 jal do_IRQ
75 j ret_from_irq
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
new file mode 100644
index 000000000000..5f027bfa4af8
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -0,0 +1,199 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5477/irq.c
6 * The irq setup and misc routines for DDB5476.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/types.h>
18#include <linux/ptrace.h>
19
20#include <asm/i8259.h>
21#include <asm/system.h>
22#include <asm/mipsregs.h>
23#include <asm/debug.h>
24#include <asm/addrspace.h>
25#include <asm/bootinfo.h>
26
27#include <asm/ddb5xxx/ddb5xxx.h>
28
29
30/*
31 * IRQ mapping
32 *
33 * 0-7: 8 CPU interrupts
34 * 0 - software interrupt 0
35 * 1 - software interrupt 1
36 * 2 - most Vrc5477 interrupts are routed to this pin
37 * 3 - (optional) some other interrupts routed to this pin for debugg
38 * 4 - not used
39 * 5 - not used
40 * 6 - not used
41 * 7 - cpu timer (used by default)
42 *
43 * 8-39: 32 Vrc5477 interrupt sources
44 * (refer to the Vrc5477 manual)
45 */
46
47#define PCI0 DDB_INTPPES0
48#define PCI1 DDB_INTPPES1
49
50#define ACTIVE_LOW 1
51#define ACTIVE_HIGH 0
52
53#define LEVEL_SENSE 2
54#define EDGE_TRIGGER 0
55
56#define INTA 0
57#define INTB 1
58#define INTC 2
59#define INTD 3
60#define INTE 4
61
62static inline void
63set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
64{
65 u32 reg_value;
66 u32 reg_bitmask;
67
68 reg_value = ddb_in32(pci);
69 reg_bitmask = 0x3 << (intn * 2);
70
71 reg_value &= ~reg_bitmask;
72 reg_value |= (active | trigger) << (intn * 2);
73 ddb_out32(pci, reg_value);
74}
75
76extern void vrc5477_irq_init(u32 base);
77extern void mips_cpu_irq_init(u32 base);
78extern asmlinkage void ddb5477_handle_int(void);
79extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
80static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
81
82void __init arch_init_irq(void)
83{
84 /* by default, we disable all interrupts and route all vrc5477
85 * interrupts to pin 0 (irq 2) */
86 ddb_out32(DDB_INTCTRL0, 0);
87 ddb_out32(DDB_INTCTRL1, 0);
88 ddb_out32(DDB_INTCTRL2, 0);
89 ddb_out32(DDB_INTCTRL3, 0);
90
91 clear_c0_status(0xff00);
92 set_c0_status(0x0400);
93
94 /* setup PCI interrupt attributes */
95 set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
96 set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
97 if (mips_machtype == MACH_NEC_ROCKHOPPERII)
98 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
99 else
100 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
101 set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
102 set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
103
104 set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
105 set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
106 set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
107 set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
108 set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
109
110 /*
111 * for debugging purpose, we enable several error interrupts
112 * and route them to pin 1. (IP3)
113 */
114 /* cpu parity check - 0 */
115 ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
116 /* cpu no-target decode - 1 */
117 ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
118 /* local bus read time-out - 7 */
119 ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
120 /* PCI SERR# - 14 */
121 ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
122 /* PCI internal error - 15 */
123 ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
124 /* IOPCI SERR# - 30 */
125 ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
126 /* IOPCI internal error - 31 */
127 ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
128
129 /* init all controllers */
130 init_i8259_irqs();
131 mips_cpu_irq_init(CPU_IRQ_BASE);
132 vrc5477_irq_init(VRC5477_IRQ_BASE);
133
134
135 /* setup cascade interrupts */
136 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
137 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
138
139 /* hook up the first-level interrupt handler */
140 set_except_vector(0, ddb5477_handle_int);
141}
142
143u8 i8259_interrupt_ack(void)
144{
145 u8 irq;
146 u32 reg;
147
148 /* Set window 0 for interrupt acknowledge */
149 reg = ddb_in32(DDB_PCIINIT10);
150
151 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
152 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
153 ddb_out32(DDB_PCIINIT10, reg);
154
155 /* i8259.c set the base vector to be 0x0 */
156 return irq + I8259_IRQ_BASE;
157}
158/*
159 * the first level int-handler will jump here if it is a vrc5477 irq
160 */
161#define NUM_5477_IRQS 32
162asmlinkage void
163vrc5477_irq_dispatch(struct pt_regs *regs)
164{
165 u32 intStatus;
166 u32 bitmask;
167 u32 i;
168
169 db_assert(ddb_in32(DDB_INT2STAT) == 0);
170 db_assert(ddb_in32(DDB_INT3STAT) == 0);
171 db_assert(ddb_in32(DDB_INT4STAT) == 0);
172 db_assert(ddb_in32(DDB_NMISTAT) == 0);
173
174 if (ddb_in32(DDB_INT1STAT) != 0) {
175#if defined(CONFIG_RUNTIME_DEBUG)
176 vrc5477_show_int_regs();
177#endif
178 panic("error interrupt has happened.");
179 }
180
181 intStatus = ddb_in32(DDB_INT0STAT);
182
183 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
184 /* check for i8259 interrupts */
185 if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
186 int i8259_irq = i8259_interrupt_ack();
187 do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
188 return;
189 }
190 }
191
192 for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
193 /* do we need to "and" with the int mask? */
194 if (intStatus & bitmask) {
195 do_IRQ(VRC5477_IRQ_BASE + i, regs);
196 return;
197 }
198 }
199}
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
new file mode 100644
index 000000000000..0d5e706207ec
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
@@ -0,0 +1,168 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5477/irq_5477.c
6 * This file defines the irq handler for Vrc5477.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15/*
16 * Vrc5477 defines 32 IRQs.
17 *
18 * This file exports one function:
19 * vrc5477_irq_init(u32 irq_base);
20 */
21
22#include <linux/interrupt.h>
23#include <linux/types.h>
24#include <linux/ptrace.h>
25
26#include <asm/debug.h>
27
28#include <asm/ddb5xxx/ddb5xxx.h>
29
30/* number of total irqs supported by Vrc5477 */
31#define NUM_5477_IRQ 32
32
33static int vrc5477_irq_base = -1;
34
35
36static void
37vrc5477_irq_enable(unsigned int irq)
38{
39 db_assert(vrc5477_irq_base != -1);
40 db_assert(irq >= vrc5477_irq_base);
41 db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
42
43 ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
44}
45
46static void
47vrc5477_irq_disable(unsigned int irq)
48{
49 db_assert(vrc5477_irq_base != -1);
50 db_assert(irq >= vrc5477_irq_base);
51 db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
52
53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
54}
55
56static unsigned int vrc5477_irq_startup(unsigned int irq)
57{
58 vrc5477_irq_enable(irq);
59 return 0;
60}
61
62#define vrc5477_irq_shutdown vrc5477_irq_disable
63
64static void
65vrc5477_irq_ack(unsigned int irq)
66{
67 db_assert(vrc5477_irq_base != -1);
68 db_assert(irq >= vrc5477_irq_base);
69 db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
70
71 /* clear the interrupt bit */
72 /* some irqs require the driver to clear the sources */
73 ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base));
74
75 /* disable interrupt - some handler will re-enable the irq
76 * and if the interrupt is leveled, we will have infinite loop
77 */
78 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
79}
80
81static void
82vrc5477_irq_end(unsigned int irq)
83{
84 db_assert(vrc5477_irq_base != -1);
85 db_assert(irq >= vrc5477_irq_base);
86 db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
87
88 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
89 ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
90}
91
92hw_irq_controller vrc5477_irq_controller = {
93 "vrc5477_irq",
94 vrc5477_irq_startup,
95 vrc5477_irq_shutdown,
96 vrc5477_irq_enable,
97 vrc5477_irq_disable,
98 vrc5477_irq_ack,
99 vrc5477_irq_end,
100 NULL /* no affinity stuff for UP */
101};
102
103void __init vrc5477_irq_init(u32 irq_base)
104{
105 u32 i;
106
107 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) {
108 irq_desc[i].status = IRQ_DISABLED;
109 irq_desc[i].action = NULL;
110 irq_desc[i].depth = 1;
111 irq_desc[i].handler = &vrc5477_irq_controller;
112 }
113
114 vrc5477_irq_base = irq_base;
115}
116
117void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
118{
119 u32 reg_value;
120 u32 reg_bitmask;
121 u32 reg_index;
122
123 db_assert(vrc5477_irq >= 0);
124 db_assert(vrc5477_irq < NUM_5477_IRQ);
125 db_assert(ip >= 0);
126 db_assert((ip < 5) || (ip == 6));
127
128 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
129 reg_value = ddb_in32(reg_index);
130 reg_bitmask = 7 << (vrc5477_irq % 8 * 4);
131 reg_value &= ~reg_bitmask;
132 reg_value |= ip << (vrc5477_irq % 8 * 4);
133 ddb_out32(reg_index, reg_value);
134}
135
136void ll_vrc5477_irq_enable(int vrc5477_irq)
137{
138 u32 reg_value;
139 u32 reg_bitmask;
140 u32 reg_index;
141
142 db_assert(vrc5477_irq >= 0);
143 db_assert(vrc5477_irq < NUM_5477_IRQ);
144
145 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
146 reg_value = ddb_in32(reg_index);
147 reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
148 db_assert((reg_value & reg_bitmask) == 0);
149 ddb_out32(reg_index, reg_value | reg_bitmask);
150}
151
152void ll_vrc5477_irq_disable(int vrc5477_irq)
153{
154 u32 reg_value;
155 u32 reg_bitmask;
156 u32 reg_index;
157
158 db_assert(vrc5477_irq >= 0);
159 db_assert(vrc5477_irq < NUM_5477_IRQ);
160
161 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
162 reg_value = ddb_in32(reg_index);
163 reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
164
165 /* we assert that the interrupt is enabled (perhaps over-zealous) */
166 db_assert( (reg_value & reg_bitmask) != 0);
167 ddb_out32(reg_index, reg_value & ~reg_bitmask);
168}
diff --git a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
new file mode 100644
index 000000000000..1d18d590495b
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
@@ -0,0 +1,136 @@
1/*
2 * kgdb io functions for DDB5477. We use the second serial port (upper one).
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* ======================= CONFIG ======================== */
15
16/* [jsun] we use the second serial port for kdb */
17#define BASE 0xbfa04240
18#define MAX_BAUD 115200
19
20/* distance in bytes between two serial registers */
21#define REG_OFFSET 8
22
23/*
24 * 0 - kgdb does serial init
25 * 1 - kgdb skip serial init
26 */
27static int remoteDebugInitialized = 0;
28
29/*
30 * the default baud rate *if* kgdb does serial init
31 */
32#define BAUD_DEFAULT UART16550_BAUD_38400
33
34/* ======================= END OF CONFIG ======================== */
35
36typedef unsigned char uint8;
37typedef unsigned int uint32;
38
39#define UART16550_BAUD_2400 2400
40#define UART16550_BAUD_4800 4800
41#define UART16550_BAUD_9600 9600
42#define UART16550_BAUD_19200 19200
43#define UART16550_BAUD_38400 38400
44#define UART16550_BAUD_57600 57600
45#define UART16550_BAUD_115200 115200
46
47#define UART16550_PARITY_NONE 0
48#define UART16550_PARITY_ODD 0x08
49#define UART16550_PARITY_EVEN 0x18
50#define UART16550_PARITY_MARK 0x28
51#define UART16550_PARITY_SPACE 0x38
52
53#define UART16550_DATA_5BIT 0x0
54#define UART16550_DATA_6BIT 0x1
55#define UART16550_DATA_7BIT 0x2
56#define UART16550_DATA_8BIT 0x3
57
58#define UART16550_STOP_1BIT 0x0
59#define UART16550_STOP_2BIT 0x4
60
61/* register offset */
62#define OFS_RCV_BUFFER 0
63#define OFS_TRANS_HOLD 0
64#define OFS_SEND_BUFFER 0
65#define OFS_INTR_ENABLE (1*REG_OFFSET)
66#define OFS_INTR_ID (2*REG_OFFSET)
67#define OFS_DATA_FORMAT (3*REG_OFFSET)
68#define OFS_LINE_CONTROL (3*REG_OFFSET)
69#define OFS_MODEM_CONTROL (4*REG_OFFSET)
70#define OFS_RS232_OUTPUT (4*REG_OFFSET)
71#define OFS_LINE_STATUS (5*REG_OFFSET)
72#define OFS_MODEM_STATUS (6*REG_OFFSET)
73#define OFS_RS232_INPUT (6*REG_OFFSET)
74#define OFS_SCRATCH_PAD (7*REG_OFFSET)
75
76#define OFS_DIVISOR_LSB (0*REG_OFFSET)
77#define OFS_DIVISOR_MSB (1*REG_OFFSET)
78
79
80/* memory-mapped read/write of the port */
81#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
82#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
83
84void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
85{
86 /* disable interrupts */
87 UART16550_WRITE(OFS_INTR_ENABLE, 0);
88
89 /* set up buad rate */
90 {
91 uint32 divisor;
92
93 /* set DIAB bit */
94 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
95
96 /* set divisor */
97 divisor = MAX_BAUD / baud;
98 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
99 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
100
101 /* clear DIAB bit */
102 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
103 }
104
105 /* set data format */
106 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
107}
108
109
110uint8 getDebugChar(void)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(BAUD_DEFAULT,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
120 return UART16550_READ(OFS_RCV_BUFFER);
121}
122
123
124int putDebugChar(uint8 byte)
125{
126 if (!remoteDebugInitialized) {
127 remoteDebugInitialized = 1;
128 debugInit(BAUD_DEFAULT,
129 UART16550_DATA_8BIT,
130 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
131 }
132
133 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
134 UART16550_WRITE(OFS_SEND_BUFFER, byte);
135 return 1;
136}
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.c b/arch/mips/ddb5xxx/ddb5477/lcd44780.c
new file mode 100644
index 000000000000..35c6c22610c5
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/lcd44780.c
@@ -0,0 +1,92 @@
1/*
2 * lcd44780.c
3 * Simple "driver" for a memory-mapped 44780-style LCD display.
4 *
5 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#define LCD44780_COMMAND ((volatile unsigned char *)0xbe020000)
15#define LCD44780_DATA ((volatile unsigned char *)0xbe020001)
16
17#define LCD44780_4BIT_1LINE 0x20
18#define LCD44780_4BIT_2LINE 0x28
19#define LCD44780_8BIT_1LINE 0x30
20#define LCD44780_8BIT_2LINE 0x38
21#define LCD44780_MODE_DEC 0x04
22#define LCD44780_MODE_DEC_SHIFT 0x05
23#define LCD44780_MODE_INC 0x06
24#define LCD44780_MODE_INC_SHIFT 0x07
25#define LCD44780_SCROLL_LEFT 0x18
26#define LCD44780_SCROLL_RIGHT 0x1e
27#define LCD44780_CURSOR_UNDERLINE 0x0e
28#define LCD44780_CURSOR_BLOCK 0x0f
29#define LCD44780_CURSOR_OFF 0x0c
30#define LCD44780_CLEAR 0x01
31#define LCD44780_BLANK 0x08
32#define LCD44780_RESTORE 0x0c // Same as CURSOR_OFF
33#define LCD44780_HOME 0x02
34#define LCD44780_LEFT 0x10
35#define LCD44780_RIGHT 0x14
36
37void lcd44780_wait(void)
38{
39 int i, j;
40 for(i=0; i < 400; i++)
41 for(j=0; j < 10000; j++);
42}
43
44void lcd44780_command(unsigned char c)
45{
46 *LCD44780_COMMAND = c;
47 lcd44780_wait();
48}
49
50void lcd44780_data(unsigned char c)
51{
52 *LCD44780_DATA = c;
53 lcd44780_wait();
54}
55
56void lcd44780_puts(const char* s)
57{
58 int i,j;
59 int pos = 0;
60
61 lcd44780_command(LCD44780_CLEAR);
62 while(*s) {
63 lcd44780_data(*s);
64 s++;
65 pos++;
66 if (pos == 8) {
67 /* We must write 32 of spaces to get cursor to 2nd line */
68 for (j=0; j<32; j++) {
69 lcd44780_data(' ');
70 }
71 }
72 if (pos == 16) {
73 /* We have filled all 16 character positions, so stop
74 outputing data */
75 break;
76 }
77 }
78#ifdef LCD44780_PUTS_PAUSE
79 for(i = 1; i < 2000; i++)
80 lcd44780_wait();
81#endif
82}
83
84void lcd44780_init(void)
85{
86 // The display on the RockHopper is physically a single
87 // 16 char line (two 8 char lines concatenated). bdl
88 lcd44780_command(LCD44780_8BIT_2LINE);
89 lcd44780_command(LCD44780_MODE_INC);
90 lcd44780_command(LCD44780_CURSOR_BLOCK);
91 lcd44780_command(LCD44780_CLEAR);
92}
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.h b/arch/mips/ddb5xxx/ddb5477/lcd44780.h
new file mode 100644
index 000000000000..cf2f0f71eee5
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/lcd44780.h
@@ -0,0 +1,15 @@
1/*
2 * lcd44780.h
3 * Simple "driver" for a memory-mapped 44780-style LCD display.
4 *
5 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14void lcd44780_puts(const char* s);
15void lcd44780_init(void);
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
new file mode 100644
index 000000000000..15c6e543b56f
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/setup.c
@@ -0,0 +1,405 @@
1/*
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
7 *
8 * arch/mips/ddb5xxx/ddb5477/setup.c
9 * Setup file for DDB5477.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/config.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/sched.h>
21#include <linux/pci.h>
22#include <linux/ide.h>
23#include <linux/fs.h>
24#include <linux/ioport.h>
25#include <linux/param.h> /* for HZ */
26#include <linux/major.h>
27#include <linux/kdev_t.h>
28#include <linux/root_dev.h>
29
30#include <asm/cpu.h>
31#include <asm/bootinfo.h>
32#include <asm/addrspace.h>
33#include <asm/time.h>
34#include <asm/bcache.h>
35#include <asm/irq.h>
36#include <asm/reboot.h>
37#include <asm/gdb-stub.h>
38#include <asm/traps.h>
39#include <asm/debug.h>
40
41#include <asm/ddb5xxx/ddb5xxx.h>
42
43#include "lcd44780.h"
44
45
46#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
47
48#define SP_TIMER_BASE DDB_SPT1CTRL_L
49#define SP_TIMER_IRQ VRC5477_IRQ_SPT1
50
51static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
52
53static void ddb_machine_restart(char *command)
54{
55 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
56
57 u32 t;
58
59 /* PCI cold reset */
60 ddb_pci_reset_bus();
61
62 /* CPU cold reset */
63 t = ddb_in32(DDB_CPUSTAT);
64 db_assert((t&1));
65 ddb_out32(DDB_CPUSTAT, t);
66
67 /* Call the PROM */
68 back_to_prom();
69}
70
71static void ddb_machine_halt(void)
72{
73 printk("DDB Vrc-5477 halted.\n");
74 while (1);
75}
76
77static void ddb_machine_power_off(void)
78{
79 printk("DDB Vrc-5477 halted. Please turn off the power.\n");
80 while (1);
81}
82
83extern void rtc_ds1386_init(unsigned long base);
84
85static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
86{
87 unsigned int freq;
88 unsigned char c;
89 unsigned int t1, t2;
90 unsigned i;
91
92 ddb_out32(SP_TIMER_BASE, 0xffffffff);
93 ddb_out32(SP_TIMER_BASE+4, 0x1);
94 ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
95
96 /* check if rtc is running */
97 c= *(volatile unsigned char*)rtc_base;
98 for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
99 if (c == *(volatile unsigned char*)rtc_base) {
100 printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
101 return 83333000;
102 }
103
104 c= *(volatile unsigned char*)rtc_base;
105 while (c == *(volatile unsigned char*)rtc_base);
106 /* we are now at the turn of 1/100th second, if no error. */
107 t1 = ddb_in32(SP_TIMER_BASE+8);
108
109 for (i=0; i< 10; i++) {
110 c= *(volatile unsigned char*)rtc_base;
111 while (c == *(volatile unsigned char*)rtc_base);
112 /* we are now at the turn of another 1/100th second */
113 t2 = ddb_in32(SP_TIMER_BASE+8);
114 }
115
116 ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
117
118 freq = (t1 - t2)*10;
119 printk("DDB bus frequency detection : %u \n", freq);
120 return freq;
121}
122
123static void __init ddb_time_init(void)
124{
125 unsigned long rtc_base;
126 unsigned int i;
127
128 /* we have ds1396 RTC chip */
129 if (mips_machtype == MACH_NEC_ROCKHOPPER
130 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
131 rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
132 } else {
133 rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
134 }
135 rtc_ds1386_init(rtc_base);
136
137 /* do we need to do run-time detection of bus speed? */
138 if (bus_frequency == 0) {
139 bus_frequency = detect_bus_frequency(rtc_base);
140 }
141
142 /* mips_hpt_frequency is 1/2 of the cpu core freq */
143 i = (read_c0_config() >> 28 ) & 7;
144 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
145 i = 4;
146 mips_hpt_frequency = bus_frequency*(i+4)/4;
147}
148
149extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
150
151static void __init ddb_timer_setup(struct irqaction *irq)
152{
153#if defined(USE_CPU_COUNTER_TIMER)
154
155 /* we are using the cpu counter for timer interrupts */
156 setup_irq(CPU_IRQ_BASE + 7, irq);
157
158#else
159
160 /* if we use Special purpose timer 1 */
161 ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
162 ddb_out32(SP_TIMER_BASE+4, 0x1);
163 setup_irq(SP_TIMER_IRQ, irq);
164
165#endif
166}
167
168static void ddb5477_board_init(void);
169
170extern struct pci_controller ddb5477_ext_controller;
171extern struct pci_controller ddb5477_io_controller;
172
173static int ddb5477_setup(void)
174{
175 /* initialize board - we don't trust the loader */
176 ddb5477_board_init();
177
178 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
179
180 board_time_init = ddb_time_init;
181 board_timer_setup = ddb_timer_setup;
182
183 _machine_restart = ddb_machine_restart;
184 _machine_halt = ddb_machine_halt;
185 _machine_power_off = ddb_machine_power_off;
186
187 /* setup resource limits */
188 ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
189 iomem_resource.end = 0xffffffff;
190
191 /* Reboot on panic */
192 panic_timeout = 180;
193
194 register_pci_controller (&ddb5477_ext_controller);
195 register_pci_controller (&ddb5477_io_controller);
196
197 return 0;
198}
199
200early_initcall(ddb5477_setup);
201
202static void __init ddb5477_board_init(void)
203{
204 /* ----------- setup PDARs ------------ */
205
206 /* SDRAM should have been set */
207 db_assert(ddb_in32(DDB_SDRAM0) ==
208 ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
209
210 /* SDRAM1 should be turned off. What is this for anyway ? */
211 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
212
213 /* Setup local bus. */
214
215 /* Flash U12 PDAR and timing. */
216 ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
217 ddb_out32(DDB_LCST0, 0x00090842);
218
219 /* We need to setup LCS1 and LCS2 differently based on the
220 board_version */
221 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
222 /* Flash U13 PDAR and timing. */
223 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
224 ddb_out32(DDB_LCST1, 0x00090842);
225
226 /* EPLD (NVRAM, switch, LCD, and mezzanie). */
227 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
228 } else {
229 /* misc */
230 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
231 /* mezzanie (?) */
232 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
233 }
234
235 /* verify VRC5477 base addr */
236 db_assert(ddb_in32(DDB_VRC5477) ==
237 ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
238
239 /* verify BOOT ROM addr */
240 db_assert(ddb_in32(DDB_BOOTCS) ==
241 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
242
243 /* setup PCI windows - window0 for MEM/config, window1 for IO */
244 ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
245 ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
246 ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
247 ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
248
249 /* ------------ reset PCI bus and BARs ----------------- */
250 ddb_pci_reset_bus();
251
252 ddb_out32(DDB_BARM010, 0x00000008);
253 ddb_out32(DDB_BARM011, 0x00000008);
254
255 ddb_out32(DDB_BARC0, 0xffffffff);
256 ddb_out32(DDB_BARM230, 0xffffffff);
257 ddb_out32(DDB_BAR00, 0xffffffff);
258 ddb_out32(DDB_BAR10, 0xffffffff);
259 ddb_out32(DDB_BAR20, 0xffffffff);
260 ddb_out32(DDB_BAR30, 0xffffffff);
261 ddb_out32(DDB_BAR40, 0xffffffff);
262 ddb_out32(DDB_BAR50, 0xffffffff);
263 ddb_out32(DDB_BARB0, 0xffffffff);
264
265 ddb_out32(DDB_BARC1, 0xffffffff);
266 ddb_out32(DDB_BARM231, 0xffffffff);
267 ddb_out32(DDB_BAR01, 0xffffffff);
268 ddb_out32(DDB_BAR11, 0xffffffff);
269 ddb_out32(DDB_BAR21, 0xffffffff);
270 ddb_out32(DDB_BAR31, 0xffffffff);
271 ddb_out32(DDB_BAR41, 0xffffffff);
272 ddb_out32(DDB_BAR51, 0xffffffff);
273 ddb_out32(DDB_BARB1, 0xffffffff);
274
275 /*
276 * We use pci master register 0 for memory space / config space
277 * And we use register 1 for IO space.
278 * Note that for memory space, we bump up the pci base address
279 * so that we have 1:1 mapping between PCI memory and cpu physical.
280 * For PCI IO space, it starts from 0 in PCI IO space but with
281 * DDB_xx_IO_BASE in CPU physical address space.
282 */
283 ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
284 DDB_PCI_ACCESS_32);
285 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
286
287 ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
288 DDB_PCI_ACCESS_32);
289 ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
290 DDB_PCI_ACCESS_32);
291
292
293 /* PCI cross window should be set properly */
294 ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
295 ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
296 ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
297 ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
298
299 if (mips_machtype == MACH_NEC_ROCKHOPPER
300 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
301 /* Disable bus diagnostics. */
302 ddb_out32(DDB_PCICTL0_L, 0);
303 ddb_out32(DDB_PCICTL0_H, 0);
304 ddb_out32(DDB_PCICTL1_L, 0);
305 ddb_out32(DDB_PCICTL1_H, 0);
306 }
307
308 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
309 u16 vid;
310 struct pci_bus bus;
311 struct pci_dev dev_m1533;
312 extern struct pci_ops ddb5477_ext_pci_ops;
313
314 bus.parent = NULL; /* we scan the top level only */
315 bus.ops = &ddb5477_ext_pci_ops;
316 dev_m1533.bus = &bus;
317 dev_m1533.sysdata = NULL;
318 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
319 pci_read_config_word(&dev_m1533, 0, &vid);
320 if (vid == PCI_VENDOR_ID_AL) {
321 printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
322 mips_machtype = MACH_NEC_ROCKHOPPERII;
323 }
324 }
325
326 /* enable USB input buffers */
327 ddb_out32(DDB_PIBMISC, 0x00000007);
328
329 /* For dual-function pins, make them all non-GPIO */
330 ddb_out32(DDB_GIUFUNSEL, 0x0);
331 // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
332
333 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
334
335 /* enable IDE controller on Ali chip (south bridge) */
336 u8 temp8;
337 struct pci_bus bus;
338 struct pci_dev dev_m1533;
339 struct pci_dev dev_m5229;
340 extern struct pci_ops ddb5477_ext_pci_ops;
341
342 /* Setup M1535 registers */
343 bus.parent = NULL; /* we scan the top level only */
344 bus.ops = &ddb5477_ext_pci_ops;
345 dev_m1533.bus = &bus;
346 dev_m1533.sysdata = NULL;
347 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
348
349 /* setup IDE controller
350 * enable IDE controller (bit 6 - 1)
351 * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
352 * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
353 * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
354 */
355 pci_write_config_byte(&dev_m1533, 0x58, 0x74);
356
357 /*
358 * positive decode (bit6 -0)
359 * enable IDE controler interrupt (bit 4 -1)
360 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
361 */
362 pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
363
364 /* Setup M5229 registers */
365 dev_m5229.bus = &bus;
366 dev_m5229.sysdata = NULL;
367 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
368
369 /*
370 * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
371 * M5229 IDSEL is addr:15; see above setting
372 */
373 pci_read_config_byte(&dev_m5229, 0x50, &temp8);
374 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
375
376 /*
377 * enable bus master (bit 2) and IO decoding (bit 0)
378 */
379 pci_read_config_byte(&dev_m5229, 0x04, &temp8);
380 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
381
382 /*
383 * enable native, copied from arch/ppc/k2boot/head.S
384 * TODO - need volatile, need to be portable
385 */
386 pci_write_config_byte(&dev_m5229, 0x09, 0xef);
387
388 /* Set Primary Channel Command Block Timing */
389 pci_write_config_byte(&dev_m5229, 0x59, 0x31);
390
391 /*
392 * Enable primary channel 40-pin cable
393 * M5229 register 0x4a (bit 0)
394 */
395 pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
396 pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
397 }
398
399 if (mips_machtype == MACH_NEC_ROCKHOPPER
400 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
401 printk("lcd44780: initializing\n");
402 lcd44780_init();
403 lcd44780_puts("MontaVista Linux");
404 }
405}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 17:17:35 -0500