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-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c405
1 files changed, 405 insertions, 0 deletions
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
new file mode 100644
index 000000000000..15c6e543b56f
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+++ b/arch/mips/ddb5xxx/ddb5477/setup.c
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1/*
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
7 *
8 * arch/mips/ddb5xxx/ddb5477/setup.c
9 * Setup file for DDB5477.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/config.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/sched.h>
21#include <linux/pci.h>
22#include <linux/ide.h>
23#include <linux/fs.h>
24#include <linux/ioport.h>
25#include <linux/param.h> /* for HZ */
26#include <linux/major.h>
27#include <linux/kdev_t.h>
28#include <linux/root_dev.h>
29
30#include <asm/cpu.h>
31#include <asm/bootinfo.h>
32#include <asm/addrspace.h>
33#include <asm/time.h>
34#include <asm/bcache.h>
35#include <asm/irq.h>
36#include <asm/reboot.h>
37#include <asm/gdb-stub.h>
38#include <asm/traps.h>
39#include <asm/debug.h>
40
41#include <asm/ddb5xxx/ddb5xxx.h>
42
43#include "lcd44780.h"
44
45
46#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
47
48#define SP_TIMER_BASE DDB_SPT1CTRL_L
49#define SP_TIMER_IRQ VRC5477_IRQ_SPT1
50
51static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
52
53static void ddb_machine_restart(char *command)
54{
55 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
56
57 u32 t;
58
59 /* PCI cold reset */
60 ddb_pci_reset_bus();
61
62 /* CPU cold reset */
63 t = ddb_in32(DDB_CPUSTAT);
64 db_assert((t&1));
65 ddb_out32(DDB_CPUSTAT, t);
66
67 /* Call the PROM */
68 back_to_prom();
69}
70
71static void ddb_machine_halt(void)
72{
73 printk("DDB Vrc-5477 halted.\n");
74 while (1);
75}
76
77static void ddb_machine_power_off(void)
78{
79 printk("DDB Vrc-5477 halted. Please turn off the power.\n");
80 while (1);
81}
82
83extern void rtc_ds1386_init(unsigned long base);
84
85static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
86{
87 unsigned int freq;
88 unsigned char c;
89 unsigned int t1, t2;
90 unsigned i;
91
92 ddb_out32(SP_TIMER_BASE, 0xffffffff);
93 ddb_out32(SP_TIMER_BASE+4, 0x1);
94 ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
95
96 /* check if rtc is running */
97 c= *(volatile unsigned char*)rtc_base;
98 for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
99 if (c == *(volatile unsigned char*)rtc_base) {
100 printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
101 return 83333000;
102 }
103
104 c= *(volatile unsigned char*)rtc_base;
105 while (c == *(volatile unsigned char*)rtc_base);
106 /* we are now at the turn of 1/100th second, if no error. */
107 t1 = ddb_in32(SP_TIMER_BASE+8);
108
109 for (i=0; i< 10; i++) {
110 c= *(volatile unsigned char*)rtc_base;
111 while (c == *(volatile unsigned char*)rtc_base);
112 /* we are now at the turn of another 1/100th second */
113 t2 = ddb_in32(SP_TIMER_BASE+8);
114 }
115
116 ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
117
118 freq = (t1 - t2)*10;
119 printk("DDB bus frequency detection : %u \n", freq);
120 return freq;
121}
122
123static void __init ddb_time_init(void)
124{
125 unsigned long rtc_base;
126 unsigned int i;
127
128 /* we have ds1396 RTC chip */
129 if (mips_machtype == MACH_NEC_ROCKHOPPER
130 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
131 rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
132 } else {
133 rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
134 }
135 rtc_ds1386_init(rtc_base);
136
137 /* do we need to do run-time detection of bus speed? */
138 if (bus_frequency == 0) {
139 bus_frequency = detect_bus_frequency(rtc_base);
140 }
141
142 /* mips_hpt_frequency is 1/2 of the cpu core freq */
143 i = (read_c0_config() >> 28 ) & 7;
144 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
145 i = 4;
146 mips_hpt_frequency = bus_frequency*(i+4)/4;
147}
148
149extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
150
151static void __init ddb_timer_setup(struct irqaction *irq)
152{
153#if defined(USE_CPU_COUNTER_TIMER)
154
155 /* we are using the cpu counter for timer interrupts */
156 setup_irq(CPU_IRQ_BASE + 7, irq);
157
158#else
159
160 /* if we use Special purpose timer 1 */
161 ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
162 ddb_out32(SP_TIMER_BASE+4, 0x1);
163 setup_irq(SP_TIMER_IRQ, irq);
164
165#endif
166}
167
168static void ddb5477_board_init(void);
169
170extern struct pci_controller ddb5477_ext_controller;
171extern struct pci_controller ddb5477_io_controller;
172
173static int ddb5477_setup(void)
174{
175 /* initialize board - we don't trust the loader */
176 ddb5477_board_init();
177
178 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
179
180 board_time_init = ddb_time_init;
181 board_timer_setup = ddb_timer_setup;
182
183 _machine_restart = ddb_machine_restart;
184 _machine_halt = ddb_machine_halt;
185 _machine_power_off = ddb_machine_power_off;
186
187 /* setup resource limits */
188 ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
189 iomem_resource.end = 0xffffffff;
190
191 /* Reboot on panic */
192 panic_timeout = 180;
193
194 register_pci_controller (&ddb5477_ext_controller);
195 register_pci_controller (&ddb5477_io_controller);
196
197 return 0;
198}
199
200early_initcall(ddb5477_setup);
201
202static void __init ddb5477_board_init(void)
203{
204 /* ----------- setup PDARs ------------ */
205
206 /* SDRAM should have been set */
207 db_assert(ddb_in32(DDB_SDRAM0) ==
208 ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
209
210 /* SDRAM1 should be turned off. What is this for anyway ? */
211 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
212
213 /* Setup local bus. */
214
215 /* Flash U12 PDAR and timing. */
216 ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
217 ddb_out32(DDB_LCST0, 0x00090842);
218
219 /* We need to setup LCS1 and LCS2 differently based on the
220 board_version */
221 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
222 /* Flash U13 PDAR and timing. */
223 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
224 ddb_out32(DDB_LCST1, 0x00090842);
225
226 /* EPLD (NVRAM, switch, LCD, and mezzanie). */
227 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
228 } else {
229 /* misc */
230 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
231 /* mezzanie (?) */
232 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
233 }
234
235 /* verify VRC5477 base addr */
236 db_assert(ddb_in32(DDB_VRC5477) ==
237 ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
238
239 /* verify BOOT ROM addr */
240 db_assert(ddb_in32(DDB_BOOTCS) ==
241 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
242
243 /* setup PCI windows - window0 for MEM/config, window1 for IO */
244 ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
245 ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
246 ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
247 ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
248
249 /* ------------ reset PCI bus and BARs ----------------- */
250 ddb_pci_reset_bus();
251
252 ddb_out32(DDB_BARM010, 0x00000008);
253 ddb_out32(DDB_BARM011, 0x00000008);
254
255 ddb_out32(DDB_BARC0, 0xffffffff);
256 ddb_out32(DDB_BARM230, 0xffffffff);
257 ddb_out32(DDB_BAR00, 0xffffffff);
258 ddb_out32(DDB_BAR10, 0xffffffff);
259 ddb_out32(DDB_BAR20, 0xffffffff);
260 ddb_out32(DDB_BAR30, 0xffffffff);
261 ddb_out32(DDB_BAR40, 0xffffffff);
262 ddb_out32(DDB_BAR50, 0xffffffff);
263 ddb_out32(DDB_BARB0, 0xffffffff);
264
265 ddb_out32(DDB_BARC1, 0xffffffff);
266 ddb_out32(DDB_BARM231, 0xffffffff);
267 ddb_out32(DDB_BAR01, 0xffffffff);
268 ddb_out32(DDB_BAR11, 0xffffffff);
269 ddb_out32(DDB_BAR21, 0xffffffff);
270 ddb_out32(DDB_BAR31, 0xffffffff);
271 ddb_out32(DDB_BAR41, 0xffffffff);
272 ddb_out32(DDB_BAR51, 0xffffffff);
273 ddb_out32(DDB_BARB1, 0xffffffff);
274
275 /*
276 * We use pci master register 0 for memory space / config space
277 * And we use register 1 for IO space.
278 * Note that for memory space, we bump up the pci base address
279 * so that we have 1:1 mapping between PCI memory and cpu physical.
280 * For PCI IO space, it starts from 0 in PCI IO space but with
281 * DDB_xx_IO_BASE in CPU physical address space.
282 */
283 ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
284 DDB_PCI_ACCESS_32);
285 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
286
287 ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
288 DDB_PCI_ACCESS_32);
289 ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
290 DDB_PCI_ACCESS_32);
291
292
293 /* PCI cross window should be set properly */
294 ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
295 ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
296 ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
297 ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
298
299 if (mips_machtype == MACH_NEC_ROCKHOPPER
300 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
301 /* Disable bus diagnostics. */
302 ddb_out32(DDB_PCICTL0_L, 0);
303 ddb_out32(DDB_PCICTL0_H, 0);
304 ddb_out32(DDB_PCICTL1_L, 0);
305 ddb_out32(DDB_PCICTL1_H, 0);
306 }
307
308 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
309 u16 vid;
310 struct pci_bus bus;
311 struct pci_dev dev_m1533;
312 extern struct pci_ops ddb5477_ext_pci_ops;
313
314 bus.parent = NULL; /* we scan the top level only */
315 bus.ops = &ddb5477_ext_pci_ops;
316 dev_m1533.bus = &bus;
317 dev_m1533.sysdata = NULL;
318 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
319 pci_read_config_word(&dev_m1533, 0, &vid);
320 if (vid == PCI_VENDOR_ID_AL) {
321 printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
322 mips_machtype = MACH_NEC_ROCKHOPPERII;
323 }
324 }
325
326 /* enable USB input buffers */
327 ddb_out32(DDB_PIBMISC, 0x00000007);
328
329 /* For dual-function pins, make them all non-GPIO */
330 ddb_out32(DDB_GIUFUNSEL, 0x0);
331 // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
332
333 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
334
335 /* enable IDE controller on Ali chip (south bridge) */
336 u8 temp8;
337 struct pci_bus bus;
338 struct pci_dev dev_m1533;
339 struct pci_dev dev_m5229;
340 extern struct pci_ops ddb5477_ext_pci_ops;
341
342 /* Setup M1535 registers */
343 bus.parent = NULL; /* we scan the top level only */
344 bus.ops = &ddb5477_ext_pci_ops;
345 dev_m1533.bus = &bus;
346 dev_m1533.sysdata = NULL;
347 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
348
349 /* setup IDE controller
350 * enable IDE controller (bit 6 - 1)
351 * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
352 * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
353 * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
354 */
355 pci_write_config_byte(&dev_m1533, 0x58, 0x74);
356
357 /*
358 * positive decode (bit6 -0)
359 * enable IDE controler interrupt (bit 4 -1)
360 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
361 */
362 pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
363
364 /* Setup M5229 registers */
365 dev_m5229.bus = &bus;
366 dev_m5229.sysdata = NULL;
367 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
368
369 /*
370 * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
371 * M5229 IDSEL is addr:15; see above setting
372 */
373 pci_read_config_byte(&dev_m5229, 0x50, &temp8);
374 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
375
376 /*
377 * enable bus master (bit 2) and IO decoding (bit 0)
378 */
379 pci_read_config_byte(&dev_m5229, 0x04, &temp8);
380 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
381
382 /*
383 * enable native, copied from arch/ppc/k2boot/head.S
384 * TODO - need volatile, need to be portable
385 */
386 pci_write_config_byte(&dev_m5229, 0x09, 0xef);
387
388 /* Set Primary Channel Command Block Timing */
389 pci_write_config_byte(&dev_m5229, 0x59, 0x31);
390
391 /*
392 * Enable primary channel 40-pin cable
393 * M5229 register 0x4a (bit 0)
394 */
395 pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
396 pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
397 }
398
399 if (mips_machtype == MACH_NEC_ROCKHOPPER
400 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
401 printk("lcd44780: initializing\n");
402 lcd44780_init();
403 lcd44780_puts("MontaVista Linux");
404 }
405}
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