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Diffstat (limited to 'arch/mips/ddb5xxx/ddb5477/irq.c')
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c24
1 files changed, 19 insertions, 5 deletions
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
index 9ffe1a9142ca..de433cf9fb50 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -75,7 +75,6 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
75 75
76extern void vrc5477_irq_init(u32 base); 76extern void vrc5477_irq_init(u32 base);
77extern void mips_cpu_irq_init(u32 base); 77extern void mips_cpu_irq_init(u32 base);
78extern asmlinkage void ddb5477_handle_int(void);
79extern int setup_irq(unsigned int irq, struct irqaction *irqaction); 78extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
80static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; 79static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
81 80
@@ -135,9 +134,6 @@ void __init arch_init_irq(void)
135 /* setup cascade interrupts */ 134 /* setup cascade interrupts */
136 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); 135 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
137 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); 136 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
138
139 /* hook up the first-level interrupt handler */
140 set_except_vector(0, ddb5477_handle_int);
141} 137}
142 138
143u8 i8259_interrupt_ack(void) 139u8 i8259_interrupt_ack(void)
@@ -159,7 +155,7 @@ u8 i8259_interrupt_ack(void)
159 * the first level int-handler will jump here if it is a vrc5477 irq 155 * the first level int-handler will jump here if it is a vrc5477 irq
160 */ 156 */
161#define NUM_5477_IRQS 32 157#define NUM_5477_IRQS 32
162asmlinkage void 158static void
163vrc5477_irq_dispatch(struct pt_regs *regs) 159vrc5477_irq_dispatch(struct pt_regs *regs)
164{ 160{
165 u32 intStatus; 161 u32 intStatus;
@@ -197,3 +193,21 @@ vrc5477_irq_dispatch(struct pt_regs *regs)
197 } 193 }
198 } 194 }
199} 195}
196
197#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
198
199asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
200{
201 unsigned int pending = read_c0_cause() & read_c0_status();
202
203 if (pending & STATUSF_IP7)
204 do_IRQ(CPU_IRQ_BASE + 7, regs);
205 else if (pending & VR5477INTS)
206 vrc5477_irq_dispatch(regs);
207 else if (pending & STATUSF_IP0)
208 do_IRQ(CPU_IRQ_BASE, regs);
209 else if (pending & STATUSF_IP1)
210 do_IRQ(CPU_IRQ_BASE + 1, regs);
211 else
212 spurious_interrupt(regs);
213}