aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/ddb5xxx/ddb5476/setup.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/ddb5xxx/ddb5476/setup.c')
-rw-r--r--arch/mips/ddb5xxx/ddb5476/setup.c296
1 files changed, 0 insertions, 296 deletions
diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c
deleted file mode 100644
index c902adef5942..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/setup.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/pm.h>
15
16#include <asm/addrspace.h>
17#include <asm/bcache.h>
18#include <asm/irq.h>
19#include <asm/reboot.h>
20#include <asm/gdb-stub.h>
21#include <asm/time.h>
22#include <asm/debug.h>
23#include <asm/traps.h>
24
25#include <asm/ddb5xxx/ddb5xxx.h>
26
27// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
28
29#ifdef USE_CPU_COUNTER_TIMER
30
31#define CPU_COUNTER_FREQUENCY 83000000
32#else
33/* otherwise we use general purpose timer */
34#define TIMER_FREQUENCY 83000000
35#define TIMER_BASE DDB_T2CTRL
36#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
37#endif
38
39static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
40
41static void ddb_machine_restart(char *command)
42{
43 u32 t;
44
45 /* PCI cold reset */
46 t = ddb_in32(DDB_PCICTRL + 4);
47 t |= 0x40000000;
48 ddb_out32(DDB_PCICTRL + 4, t);
49 /* CPU cold reset */
50 t = ddb_in32(DDB_CPUSTAT);
51 t |= 1;
52 ddb_out32(DDB_CPUSTAT, t);
53 /* Call the PROM */
54 back_to_prom();
55}
56
57static void ddb_machine_halt(void)
58{
59 printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
60 while (1);
61}
62
63static void ddb_machine_power_off(void)
64{
65 printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
66 while (1);
67}
68
69extern void rtc_ds1386_init(unsigned long base);
70
71static void __init ddb_time_init(void)
72{
73#if defined(USE_CPU_COUNTER_TIMER)
74 mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
75#endif
76
77 /* we have ds1396 RTC chip */
78 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
79}
80
81
82extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
83static void __init ddb_timer_setup(struct irqaction *irq)
84{
85#if defined(USE_CPU_COUNTER_TIMER)
86
87 unsigned int count;
88
89 /* we are using the cpu counter for timer interrupts */
90 setup_irq(CPU_IRQ_BASE + 7, irq);
91
92 /* to generate the first timer interrupt */
93 count = read_c0_count();
94 write_c0_compare(count + 1000);
95
96#else
97
98 ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
99 ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */
100 setup_irq(TIMER_IRQ, irq);
101#endif
102}
103
104static struct {
105 struct resource dma1;
106 struct resource timer;
107 struct resource rtc;
108 struct resource dma_page_reg;
109 struct resource dma2;
110} ddb5476_ioport = {
111 {
112 "dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
113 "timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
114 "rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
115 "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
116 "dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
117};
118
119static struct {
120 struct resource nile4;
121} ddb5476_iomem = {
122 { "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
123};
124
125
126static void ddb5476_board_init(void);
127
128void __init plat_setup(void)
129{
130 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
131
132 board_time_init = ddb_time_init;
133 board_timer_setup = ddb_timer_setup;
134
135 _machine_restart = ddb_machine_restart;
136 _machine_halt = ddb_machine_halt;
137 pm_power_off = ddb_machine_power_off;
138
139 /* request io port/mem resources */
140 if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
141 request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
142 request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
143 request_resource(&ioport_resource,
144 &ddb5476_ioport.dma_page_reg)
145 || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
146 || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
147 printk
148 ("ddb_setup - requesting oo port resources failed.\n");
149 for (;;);
150 }
151
152 /* Reboot on panic */
153 panic_timeout = 180;
154
155 /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
156 /* *(long*)0xbfa00218 = 0x8; */
157
158 /* board initialization stuff */
159 ddb5476_board_init();
160}
161
162/*
163 * We don't trust bios. We essentially does hardware re-initialization
164 * as complete as possible, as far as we know we can safely do.
165 */
166static void ddb5476_board_init(void)
167{
168 /* ----------- setup PDARs ------------ */
169 /* check SDRAM0, whether we are on MEM bus does not matter */
170 db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
171 ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
172
173 /* SDRAM1 should be turned off. What is this for anyway ? */
174 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
175
176 /* flash 1&2, DDB status, DDB control */
177 ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
178 ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
179 ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
180 ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
181
182 /* shut off other pdar so they don't accidentally get into the way */
183 ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
184 ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
185 ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
186
187 /* verify VRC5477 base addr */
188 /* don't care about some details */
189 db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
190 ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
191
192 /* verify BOOT ROM addr */
193 /* don't care about some details */
194 db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
195 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
196
197 /* setup PCI windows - window1 for MEM/config, window0 for IO */
198 ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
199 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
200
201 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
202 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
203
204 /* ----------- setup PDARs ------------ */
205 /* this is problematic - it will reset Aladin which cause we loose
206 * serial port, and we don't know how to set up Aladin chip again.
207 */
208 // ddb_pci_reset_bus();
209
210 ddb_out32(DDB_BAR0, 0x00000008);
211
212 ddb_out32(DDB_BARC, 0xffffffff);
213 ddb_out32(DDB_BARB, 0xffffffff);
214 ddb_out32(DDB_BAR1, 0xffffffff);
215 ddb_out32(DDB_BAR2, 0xffffffff);
216 ddb_out32(DDB_BAR3, 0xffffffff);
217 ddb_out32(DDB_BAR4, 0xffffffff);
218 ddb_out32(DDB_BAR5, 0xffffffff);
219 ddb_out32(DDB_BAR6, 0xffffffff);
220 ddb_out32(DDB_BAR7, 0xffffffff);
221 ddb_out32(DDB_BAR8, 0xffffffff);
222
223 /* ----------- switch PCI1 to PCI CONFIG space ------------ */
224 ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
225 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
226
227 /* ----- M1543 PCI setup ------ */
228
229 /* we know M1543 PCI-ISA controller is at addr:18 */
230 /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
231 *(volatile unsigned char *) 0xa8040072 &= 0xf0;
232 *(volatile unsigned char *) 0xa8040072 |= 0xa;
233
234 /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
235 * no IOCHRDY signal, (bit 7 - 1)
236 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
237 * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
238 */
239 *(unsigned char *) 0xa8040074 = 0xd1;
240
241 /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
242 * SCI routing to IRQ 13 disabled (bit 7 - 1)
243 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
244 */
245 *(unsigned char *) 0xa8040076 = 0x83;
246
247 /* setup IDE controller
248 * enable IDE controller (bit 6 - 1)
249 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
250 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
251 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
252 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
253 */
254 // *(unsigned char*)0xa8040058 = 0x71;
255 // *(unsigned char*)0xa8040058 = 0x79;
256 // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state
257 *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state
258
259#if 0
260 /* this is not necessary if M5229 does not use SIRQ */
261 *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14
262 *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14
263#endif
264
265 /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
266 /* M5229 IDSEL is addr:24; see above setting */
267 *(unsigned char *) 0xa9000050 |= 0x1;
268
269 /* enable bus master (bit 2) and IO decoding (bit 0) */
270 *(unsigned char *) 0xa9000004 |= 0x5;
271
272 /* enable native, copied from arch/ppc/k2boot/head.S */
273 /* TODO - need volatile, need to be portable */
274 *(unsigned char *) 0xa9000009 = 0xff;
275
276 /* ----- end of M1543 PCI setup ------ */
277
278 /* ----- reset on-board ether chip ------ */
279 *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */
280 *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */
281
282 /* send reset command */
283 *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */
284
285 /* disable ether chip */
286 *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */
287
288 /* put it into sleep */
289 *((volatile u32 *) 0xa8020040) = 0x80000000;
290
291 /* ----- end of reset on-board ether chip ------ */
292
293 /* ----------- switch PCI1 back to PCI MEM space ------------ */
294 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
295 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
296}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 17:01:18 -0500