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-rw-r--r--arch/mips/ddb5xxx/ddb5476/setup.c321
1 files changed, 0 insertions, 321 deletions
diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c
deleted file mode 100644
index 101021afb2e4..000000000000
--- a/arch/mips/ddb5xxx/ddb5476/setup.c
+++ /dev/null
@@ -1,321 +0,0 @@
1/*
2 * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/pm.h>
15
16#include <asm/addrspace.h>
17#include <asm/bcache.h>
18#include <asm/irq.h>
19#include <asm/reboot.h>
20#include <asm/gdb-stub.h>
21#include <asm/time.h>
22#include <asm/debug.h>
23#include <asm/traps.h>
24
25#include <asm/ddb5xxx/ddb5xxx.h>
26
27// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
28
29#ifdef USE_CPU_COUNTER_TIMER
30
31#define CPU_COUNTER_FREQUENCY 83000000
32#else
33/* otherwise we use general purpose timer */
34#define TIMER_FREQUENCY 83000000
35#define TIMER_BASE DDB_T2CTRL
36#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
37#endif
38
39static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
40
41static void ddb_machine_restart(char *command)
42{
43 u32 t;
44
45 /* PCI cold reset */
46 t = ddb_in32(DDB_PCICTRL + 4);
47 t |= 0x40000000;
48 ddb_out32(DDB_PCICTRL + 4, t);
49 /* CPU cold reset */
50 t = ddb_in32(DDB_CPUSTAT);
51 t |= 1;
52 ddb_out32(DDB_CPUSTAT, t);
53 /* Call the PROM */
54 back_to_prom();
55}
56
57static void ddb_machine_halt(void)
58{
59 printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
60 while (1);
61}
62
63static void ddb_machine_power_off(void)
64{
65 printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
66 while (1);
67}
68
69extern void rtc_ds1386_init(unsigned long base);
70
71static void __init ddb_time_init(void)
72{
73#if defined(USE_CPU_COUNTER_TIMER)
74 mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
75#endif
76
77 /* we have ds1396 RTC chip */
78 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
79}
80
81
82extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
83static void __init ddb_timer_setup(struct irqaction *irq)
84{
85#if defined(USE_CPU_COUNTER_TIMER)
86
87 unsigned int count;
88
89 /* we are using the cpu counter for timer interrupts */
90 setup_irq(CPU_IRQ_BASE + 7, irq);
91
92 /* to generate the first timer interrupt */
93 count = read_c0_count();
94 write_c0_compare(count + 1000);
95
96#else
97
98 ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
99 ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */
100 setup_irq(TIMER_IRQ, irq);
101#endif
102}
103
104static struct {
105 struct resource dma1;
106 struct resource timer;
107 struct resource rtc;
108 struct resource dma_page_reg;
109 struct resource dma2;
110} ddb5476_ioport = {
111 {
112 .start = 0x00,
113 .end = 0x1f,
114 .name = "dma1",
115 .flags = IORESOURCE_BUSY
116 }, {
117 .start = 0x40,
118 .end = 0x5f,
119 .name = "timer",
120 .flags = IORESOURCE_BUSY
121 }, {
122 .start = 0x70,
123 .end = 0x7f,
124 .name = "rtc",
125 .flags = IORESOURCE_BUSY
126 }, {
127 .start = 0x80,
128 .end = 0x8f,
129 .name = "dma page reg",
130 .flags = IORESOURCE_BUSY
131 }, {
132 .start = 0xc0,
133 .end = 0xdf,
134 .name = "dma2",
135 .flags = IORESOURCE_BUSY
136 }
137};
138
139static struct {
140 struct resource nile4;
141} ddb5476_iomem = {
142 {
143 .start = DDB_BASE,
144 .end = DDB_BASE + DDB_SIZE - 1,
145 .name = "Nile 4",
146 .flags = IORESOURCE_BUSY
147 }
148};
149
150
151static void ddb5476_board_init(void);
152
153void __init plat_mem_setup(void)
154{
155 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
156
157 board_time_init = ddb_time_init;
158 board_timer_setup = ddb_timer_setup;
159
160 _machine_restart = ddb_machine_restart;
161 _machine_halt = ddb_machine_halt;
162 pm_power_off = ddb_machine_power_off;
163
164 /* request io port/mem resources */
165 if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
166 request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
167 request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
168 request_resource(&ioport_resource,
169 &ddb5476_ioport.dma_page_reg)
170 || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
171 || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
172 printk
173 ("ddb_setup - requesting oo port resources failed.\n");
174 for (;;);
175 }
176
177 /* Reboot on panic */
178 panic_timeout = 180;
179
180 /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
181 /* *(long*)0xbfa00218 = 0x8; */
182
183 /* board initialization stuff */
184 ddb5476_board_init();
185}
186
187/*
188 * We don't trust bios. We essentially does hardware re-initialization
189 * as complete as possible, as far as we know we can safely do.
190 */
191static void ddb5476_board_init(void)
192{
193 /* ----------- setup PDARs ------------ */
194 /* check SDRAM0, whether we are on MEM bus does not matter */
195 db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
196 ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
197
198 /* SDRAM1 should be turned off. What is this for anyway ? */
199 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
200
201 /* flash 1&2, DDB status, DDB control */
202 ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
203 ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
204 ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
205 ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
206
207 /* shut off other pdar so they don't accidentally get into the way */
208 ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
209 ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
210 ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
211
212 /* verify VRC5477 base addr */
213 /* don't care about some details */
214 db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
215 ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
216
217 /* verify BOOT ROM addr */
218 /* don't care about some details */
219 db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
220 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
221
222 /* setup PCI windows - window1 for MEM/config, window0 for IO */
223 ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
224 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
225
226 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
227 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
228
229 /* ----------- setup PDARs ------------ */
230 /* this is problematic - it will reset Aladin which cause we loose
231 * serial port, and we don't know how to set up Aladin chip again.
232 */
233 // ddb_pci_reset_bus();
234
235 ddb_out32(DDB_BAR0, 0x00000008);
236
237 ddb_out32(DDB_BARC, 0xffffffff);
238 ddb_out32(DDB_BARB, 0xffffffff);
239 ddb_out32(DDB_BAR1, 0xffffffff);
240 ddb_out32(DDB_BAR2, 0xffffffff);
241 ddb_out32(DDB_BAR3, 0xffffffff);
242 ddb_out32(DDB_BAR4, 0xffffffff);
243 ddb_out32(DDB_BAR5, 0xffffffff);
244 ddb_out32(DDB_BAR6, 0xffffffff);
245 ddb_out32(DDB_BAR7, 0xffffffff);
246 ddb_out32(DDB_BAR8, 0xffffffff);
247
248 /* ----------- switch PCI1 to PCI CONFIG space ------------ */
249 ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
250 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
251
252 /* ----- M1543 PCI setup ------ */
253
254 /* we know M1543 PCI-ISA controller is at addr:18 */
255 /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
256 *(volatile unsigned char *) 0xa8040072 &= 0xf0;
257 *(volatile unsigned char *) 0xa8040072 |= 0xa;
258
259 /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
260 * no IOCHRDY signal, (bit 7 - 1)
261 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
262 * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
263 */
264 *(unsigned char *) 0xa8040074 = 0xd1;
265
266 /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
267 * SCI routing to IRQ 13 disabled (bit 7 - 1)
268 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
269 */
270 *(unsigned char *) 0xa8040076 = 0x83;
271
272 /* setup IDE controller
273 * enable IDE controller (bit 6 - 1)
274 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
275 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
276 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
277 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
278 */
279 // *(unsigned char*)0xa8040058 = 0x71;
280 // *(unsigned char*)0xa8040058 = 0x79;
281 // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state
282 *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state
283
284#if 0
285 /* this is not necessary if M5229 does not use SIRQ */
286 *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14
287 *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14
288#endif
289
290 /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
291 /* M5229 IDSEL is addr:24; see above setting */
292 *(unsigned char *) 0xa9000050 |= 0x1;
293
294 /* enable bus master (bit 2) and IO decoding (bit 0) */
295 *(unsigned char *) 0xa9000004 |= 0x5;
296
297 /* enable native, copied from arch/ppc/k2boot/head.S */
298 /* TODO - need volatile, need to be portable */
299 *(unsigned char *) 0xa9000009 = 0xff;
300
301 /* ----- end of M1543 PCI setup ------ */
302
303 /* ----- reset on-board ether chip ------ */
304 *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */
305 *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */
306
307 /* send reset command */
308 *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */
309
310 /* disable ether chip */
311 *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */
312
313 /* put it into sleep */
314 *((volatile u32 *) 0xa8020040) = 0x80000000;
315
316 /* ----- end of reset on-board ether chip ------ */
317
318 /* ----------- switch PCI1 back to PCI MEM space ------------ */
319 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
320 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
321}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 04:30:56 -0500