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-rw-r--r--arch/mips/ddb5xxx/ddb5074/setup.c234
1 files changed, 0 insertions, 234 deletions
diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c
deleted file mode 100644
index 91456b068c2e..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/setup.c
+++ /dev/null
@@ -1,234 +0,0 @@
1/*
2 * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/ide.h>
15#include <linux/ioport.h>
16#include <linux/irq.h>
17#include <linux/pm.h>
18
19#include <asm/addrspace.h>
20#include <asm/bcache.h>
21#include <asm/irq.h>
22#include <asm/reboot.h>
23#include <asm/gdb-stub.h>
24#include <asm/time.h>
25#include <asm/nile4.h>
26#include <asm/ddb5xxx/ddb5074.h>
27#include <asm/ddb5xxx/ddb5xxx.h>
28
29static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
30
31static void ddb_machine_restart(char *command)
32{
33 u32 t;
34
35 /* PCI cold reset */
36 t = nile4_in32(NILE4_PCICTRL + 4);
37 t |= 0x40000000;
38 nile4_out32(NILE4_PCICTRL + 4, t);
39 /* CPU cold reset */
40 t = nile4_in32(NILE4_CPUSTAT);
41 t |= 1;
42 nile4_out32(NILE4_CPUSTAT, t);
43 /* Call the PROM */
44 back_to_prom();
45}
46
47static void ddb_machine_halt(void)
48{
49 printk("DDB Vrc-5074 halted.\n");
50 do {
51 } while (1);
52}
53
54static void ddb_machine_power_off(void)
55{
56 printk("DDB Vrc-5074 halted. Please turn off the power.\n");
57 do {
58 } while (1);
59}
60
61extern void rtc_ds1386_init(unsigned long base);
62
63extern void (*board_timer_setup) (struct irqaction * irq);
64
65static void __init ddb_timer_init(struct irqaction *irq)
66{
67 /* set the clock to 1 Hz */
68 nile4_out32(NILE4_T2CTRL, 1000000);
69 /* enable the General-Purpose Timer */
70 nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
71 /* reset timer */
72 nile4_out32(NILE4_T2CNTR, 0);
73 /* enable interrupt */
74 setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
75 nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
76 change_c0_status(ST0_IM,
77 IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
78
79}
80
81static void __init ddb_time_init(void)
82{
83 /* we have ds1396 RTC chip */
84 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
85}
86
87
88
89void __init plat_setup(void)
90{
91 set_io_port_base(NILE4_PCI_IO_BASE);
92 isa_slot_offset = NILE4_PCI_MEM_BASE;
93 board_timer_setup = ddb_timer_init;
94 board_time_init = ddb_time_init;
95
96
97 _machine_restart = ddb_machine_restart;
98 _machine_halt = ddb_machine_halt;
99 pm_power_off = ddb_machine_power_off;
100
101 ddb_out32(DDB_BAR0, 0);
102
103 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10);
104 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
105
106 /* Reboot on panic */
107 panic_timeout = 180;
108}
109
110#define USE_NILE4_SERIAL 0
111
112#if USE_NILE4_SERIAL
113#define ns16550_in(reg) nile4_in8((reg)*8)
114#define ns16550_out(reg, val) nile4_out8((reg)*8, (val))
115#else
116#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8)
117static inline u8 ns16550_in(u32 reg)
118{
119 return *(volatile u8 *) (NS16550_BASE + reg);
120}
121
122static inline void ns16550_out(u32 reg, u8 val)
123{
124 *(volatile u8 *) (NS16550_BASE + reg) = val;
125}
126#endif
127
128#define NS16550_RBR 0
129#define NS16550_THR 0
130#define NS16550_DLL 0
131#define NS16550_IER 1
132#define NS16550_DLM 1
133#define NS16550_FCR 2
134#define NS16550_IIR 2
135#define NS16550_LCR 3
136#define NS16550_MCR 4
137#define NS16550_LSR 5
138#define NS16550_MSR 6
139#define NS16550_SCR 7
140
141#define NS16550_LSR_DR 0x01 /* Data ready */
142#define NS16550_LSR_OE 0x02 /* Overrun */
143#define NS16550_LSR_PE 0x04 /* Parity error */
144#define NS16550_LSR_FE 0x08 /* Framing error */
145#define NS16550_LSR_BI 0x10 /* Break */
146#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */
147#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */
148#define NS16550_LSR_ERR 0x80 /* Error */
149
150
151void _serinit(void)
152{
153#if USE_NILE4_SERIAL
154 ns16550_out(NS16550_LCR, 0x80);
155 ns16550_out(NS16550_DLM, 0x00);
156 ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */
157 ns16550_out(NS16550_LCR, 0x00);
158 ns16550_out(NS16550_LCR, 0x03);
159 ns16550_out(NS16550_FCR, 0x47);
160#else
161 /* done by PMON */
162#endif
163}
164
165void _putc(char c)
166{
167 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
168 ns16550_out(NS16550_THR, c);
169 if (c == '\n') {
170 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
171 ns16550_out(NS16550_THR, '\r');
172 }
173}
174
175void _puts(const char *s)
176{
177 char c;
178 while ((c = *s++))
179 _putc(c);
180}
181
182char _getc(void)
183{
184 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
185 return ns16550_in(NS16550_RBR);
186}
187
188int _testc(void)
189{
190 return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
191}
192
193
194/*
195 * Hexadecimal 7-segment LED
196 */
197void ddb5074_led_hex(int hex)
198{
199 outb(hex, 0x80);
200}
201
202
203/*
204 * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
205 */
206struct pci_dev *pci_pmu = NULL;
207
208void ddb5074_led_d2(int on)
209{
210 u8 t;
211
212 if (pci_pmu) {
213 pci_read_config_byte(pci_pmu, 0x7e, &t);
214 if (on)
215 t &= 0x7f;
216 else
217 t |= 0x80;
218 pci_write_config_byte(pci_pmu, 0x7e, t);
219 }
220}
221
222void ddb5074_led_d3(int on)
223{
224 u8 t;
225
226 if (pci_pmu) {
227 pci_read_config_byte(pci_pmu, 0x7e, &t);
228 if (on)
229 t &= 0xbf;
230 else
231 t |= 0x40;
232 pci_write_config_byte(pci_pmu, 0x7e, t);
233 }
234}
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