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-rw-r--r--arch/mips/ddb5xxx/ddb5074/irq.c169
1 files changed, 0 insertions, 169 deletions
diff --git a/arch/mips/ddb5xxx/ddb5074/irq.c b/arch/mips/ddb5xxx/ddb5074/irq.c
deleted file mode 100644
index 60c087b7738c..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/irq.c
+++ /dev/null
@@ -1,169 +0,0 @@
1/*
2 * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/irq.h>
9#include <linux/signal.h>
10#include <linux/sched.h>
11#include <linux/types.h>
12#include <linux/interrupt.h>
13#include <linux/ioport.h>
14
15#include <asm/i8259.h>
16#include <asm/io.h>
17#include <asm/irq_cpu.h>
18#include <asm/ptrace.h>
19#include <asm/nile4.h>
20#include <asm/ddb5xxx/ddb5xxx.h>
21#include <asm/ddb5xxx/ddb5074.h>
22
23
24static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
25
26#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
27#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
28#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
29
30#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
31#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
32#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
33
34#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
35#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
36
37#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
38#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
39
40#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
41#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
42
43
44static void m1543_irq_setup(void)
45{
46 /*
47 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
48 * the possible IO sources in the M1543 are in use by us. We will
49 * use the following mapping:
50 *
51 * IRQ1 - keyboard (default set by M1543)
52 * IRQ3 - reserved for UART B (default set by M1543) (note that
53 * the schematics for the DDB Vrc-5074 board seem to
54 * indicate that IRQ3 is connected to the DS1386
55 * watchdog timer interrupt output so we might have
56 * a conflict)
57 * IRQ4 - reserved for UART A (default set by M1543)
58 * IRQ5 - parallel (default set by M1543)
59 * IRQ8 - DS1386 time of day (RTC) interrupt
60 * IRQ12 - mouse
61 */
62
63 /*
64 * Assing mouse interrupt to IRQ12
65 */
66
67 /* Enter configuration mode */
68 outb(0x51, M1543_PNP_CONFIG);
69 outb(0x23, M1543_PNP_CONFIG);
70
71 /* Select logical device 7 (Keyboard) */
72 outb(0x07, M1543_PNP_INDEX);
73 outb(0x07, M1543_PNP_DATA);
74
75 /* Select IRQ12 */
76 outb(0x72, M1543_PNP_INDEX);
77 outb(0x0c, M1543_PNP_DATA);
78
79 outb(0x30, M1543_PNP_INDEX);
80 printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
81
82 outb(0x70, M1543_PNP_INDEX);
83 printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
84
85 /* Leave configration mode */
86 outb(0xbb, M1543_PNP_CONFIG);
87
88
89}
90
91static void ddb_local0_irqdispatch(struct pt_regs *regs)
92{
93 u32 mask;
94 int nile4_irq;
95
96 mask = nile4_get_irq_stat(0);
97
98 /* Handle the timer interrupt first */
99#if 0
100 if (mask & (1 << NILE4_INT_GPT)) {
101 do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
102 mask &= ~(1 << NILE4_INT_GPT);
103 }
104#endif
105 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
106 if (mask & 1) {
107 if (nile4_irq == NILE4_INT_INTE) {
108 int i8259_irq;
109
110 nile4_clear_irq(NILE4_INT_INTE);
111 i8259_irq = nile4_i8259_iack();
112 do_IRQ(i8259_irq, regs);
113 } else
114 do_IRQ(nile4_to_irq(nile4_irq), regs);
115
116 }
117}
118
119static void ddb_local1_irqdispatch(void)
120{
121 printk("ddb_local1_irqdispatch called\n");
122}
123
124static void ddb_buserror_irq(void)
125{
126 printk("ddb_buserror_irq called\n");
127}
128
129static void ddb_8254timer_irq(void)
130{
131 printk("ddb_8254timer_irq called\n");
132}
133
134asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
135{
136 unsigned int pending = read_c0_cause() & read_c0_status();
137
138 if (pending & CAUSEF_IP2)
139 ddb_local0_irqdispatch(regs);
140 else if (pending & CAUSEF_IP3)
141 ddb_local1_irqdispatch();
142 else if (pending & CAUSEF_IP6)
143 ddb_buserror_irq();
144 else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
145 ddb_8254timer_irq();
146}
147
148void __init arch_init_irq(void)
149{
150 /* setup cascade interrupts */
151 setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
152 setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
153
154 nile4_irq_setup(NILE4_IRQ_BASE);
155 m1543_irq_setup();
156 init_i8259_irqs();
157
158
159 printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
160
161 mips_cpu_irq_init(CPU_IRQ_BASE);
162
163 printk("enabling 8259 cascade\n");
164
165 ddb5074_led_hex(0);
166
167 /* Enable the interrupt cascade */
168 nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
169}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 16:16:00 -0500