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-rw-r--r--arch/mips/cobalt/irq.c118
-rw-r--r--arch/mips/cobalt/rtc.c5
-rw-r--r--arch/mips/cobalt/serial.c7
-rw-r--r--arch/mips/cobalt/setup.c9
4 files changed, 41 insertions, 98 deletions
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 48763cd10eaa..ac4fb912649d 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -15,104 +15,48 @@
15 15
16#include <asm/i8259.h> 16#include <asm/i8259.h>
17#include <asm/irq_cpu.h> 17#include <asm/irq_cpu.h>
18#include <asm/irq_gt641xx.h>
18#include <asm/gt64120.h> 19#include <asm/gt64120.h>
19 20
20#include <cobalt.h> 21#include <irq.h>
21
22/*
23 * We have two types of interrupts that we handle, ones that come in through
24 * the CPU interrupt lines, and ones that come in on the via chip. The CPU
25 * mappings are:
26 *
27 * 16 - Software interrupt 0 (unused) IE_SW0
28 * 17 - Software interrupt 1 (unused) IE_SW1
29 * 18 - Galileo chip (timer) IE_IRQ0
30 * 19 - Tulip 0 + NCR SCSI IE_IRQ1
31 * 20 - Tulip 1 IE_IRQ2
32 * 21 - 16550 UART IE_IRQ3
33 * 22 - VIA southbridge PIC IE_IRQ4
34 * 23 - unused IE_IRQ5
35 *
36 * The VIA chip is a master/slave 8259 setup and has the following interrupts:
37 *
38 * 8 - RTC
39 * 9 - PCI
40 * 14 - IDE0
41 * 15 - IDE1
42 */
43
44static inline void galileo_irq(void)
45{
46 unsigned int mask, pending, devfn;
47
48 mask = GT_READ(GT_INTRMASK_OFS);
49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
50
51 if (pending & GT_INTR_T0EXP_MSK) {
52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
53 do_IRQ(COBALT_GALILEO_IRQ);
54 } else if (pending & GT_INTR_RETRYCTR0_MSK) {
55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
57 printk(KERN_WARNING
58 "Galileo: PCI retry count exceeded (%02x.%u)\n",
59 PCI_SLOT(devfn), PCI_FUNC(devfn));
60 } else {
61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
62 printk(KERN_WARNING
63 "Galileo: masking unexpected interrupt %08x\n", pending);
64 }
65}
66
67static inline void via_pic_irq(void)
68{
69 int irq;
70
71 irq = i8259_irq();
72 if (irq >= 0)
73 do_IRQ(irq);
74}
75 22
76asmlinkage void plat_irq_dispatch(void) 23asmlinkage void plat_irq_dispatch(void)
77{ 24{
78 unsigned pending = read_c0_status() & read_c0_cause(); 25 unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
26 int irq;
79 27
80 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ 28 if (pending & CAUSEF_IP2)
81 galileo_irq(); 29 gt641xx_irq_dispatch();
82 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ 30 else if (pending & CAUSEF_IP6) {
83 via_pic_irq(); 31 irq = i8259_irq();
84 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ 32 if (irq < 0)
85 do_IRQ(COBALT_CPU_IRQ + 3); 33 spurious_interrupt();
86 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ 34 else
87 do_IRQ(COBALT_CPU_IRQ + 4); 35 do_IRQ(irq);
88 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ 36 } else if (pending & CAUSEF_IP3)
89 do_IRQ(COBALT_CPU_IRQ + 5); 37 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
90 else if (pending & CAUSEF_IP7) /* IRQ 23 */ 38 else if (pending & CAUSEF_IP4)
91 do_IRQ(COBALT_CPU_IRQ + 7); 39 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
40 else if (pending & CAUSEF_IP5)
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
42 else if (pending & CAUSEF_IP7)
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
44 else
45 spurious_interrupt();
92} 46}
93 47
94static struct irqaction irq_via = { 48static struct irqaction cascade = {
95 .handler = no_action, 49 .handler = no_action,
96 .mask = CPU_MASK_NONE, 50 .mask = CPU_MASK_NONE,
97 .name = "cascade" 51 .name = "cascade",
98}; 52};
99 53
100void __init arch_init_irq(void) 54void __init arch_init_irq(void)
101{ 55{
102 /* 56 mips_cpu_irq_init();
103 * Mask all Galileo interrupts. The Galileo 57 gt641xx_irq_init();
104 * handler is set in cobalt_timer_setup() 58 init_i8259_irqs();
105 */
106 GT_WRITE(GT_INTRMASK_OFS, 0);
107
108 init_i8259_irqs(); /* 0 ... 15 */
109 mips_cpu_irq_init(); /* 16 ... 23 */
110
111 /*
112 * Mask all cpu interrupts
113 * (except IE4, we already masked those at VIA level)
114 */
115 change_c0_status(ST0_IM, IE_IRQ4);
116 59
117 setup_irq(COBALT_VIA_IRQ, &irq_via); 60 setup_irq(GT641XX_CASCADE_IRQ, &cascade);
61 setup_irq(I8259_CASCADE_IRQ, &cascade);
118} 62}
diff --git a/arch/mips/cobalt/rtc.c b/arch/mips/cobalt/rtc.c
index 284daefc5c55..e70794b8bcba 100644
--- a/arch/mips/cobalt/rtc.c
+++ b/arch/mips/cobalt/rtc.c
@@ -20,6 +20,7 @@
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/mc146818rtc.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24 25
25static struct resource cobalt_rtc_resource[] __initdata = { 26static struct resource cobalt_rtc_resource[] __initdata = {
@@ -29,8 +30,8 @@ static struct resource cobalt_rtc_resource[] __initdata = {
29 .flags = IORESOURCE_IO, 30 .flags = IORESOURCE_IO,
30 }, 31 },
31 { 32 {
32 .start = 8, 33 .start = RTC_IRQ,
33 .end = 8, 34 .end = RTC_IRQ,
34 .flags = IORESOURCE_IRQ, 35 .flags = IORESOURCE_IRQ,
35 }, 36 },
36}; 37};
diff --git a/arch/mips/cobalt/serial.c b/arch/mips/cobalt/serial.c
index 08e739704cc9..53b8d0d6da90 100644
--- a/arch/mips/cobalt/serial.c
+++ b/arch/mips/cobalt/serial.c
@@ -24,6 +24,7 @@
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25 25
26#include <cobalt.h> 26#include <cobalt.h>
27#include <irq.h>
27 28
28static struct resource cobalt_uart_resource[] __initdata = { 29static struct resource cobalt_uart_resource[] __initdata = {
29 { 30 {
@@ -32,15 +33,15 @@ static struct resource cobalt_uart_resource[] __initdata = {
32 .flags = IORESOURCE_MEM, 33 .flags = IORESOURCE_MEM,
33 }, 34 },
34 { 35 {
35 .start = COBALT_SERIAL_IRQ, 36 .start = SERIAL_IRQ,
36 .end = COBALT_SERIAL_IRQ, 37 .end = SERIAL_IRQ,
37 .flags = IORESOURCE_IRQ, 38 .flags = IORESOURCE_IRQ,
38 }, 39 },
39}; 40};
40 41
41static struct plat_serial8250_port cobalt_serial8250_port[] = { 42static struct plat_serial8250_port cobalt_serial8250_port[] = {
42 { 43 {
43 .irq = COBALT_SERIAL_IRQ, 44 .irq = SERIAL_IRQ,
44 .uartclk = 18432000, 45 .uartclk = 18432000,
45 .iotype = UPIO_MEM, 46 .iotype = UPIO_MEM,
46 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 47 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index 7abe45e78425..fc9cbb251edc 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -20,6 +20,7 @@
20#include <asm/gt64120.h> 20#include <asm/gt64120.h>
21 21
22#include <cobalt.h> 22#include <cobalt.h>
23#include <irq.h>
23 24
24extern void cobalt_machine_restart(char *command); 25extern void cobalt_machine_restart(char *command);
25extern void cobalt_machine_halt(void); 26extern void cobalt_machine_halt(void);
@@ -45,14 +46,10 @@ void __init plat_timer_setup(struct irqaction *irq)
45 /* Load timer value for HZ (TCLK is 50MHz) */ 46 /* Load timer value for HZ (TCLK is 50MHz) */
46 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); 47 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
47 48
48 /* Enable timer */ 49 /* Enable timer0 */
49 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 50 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
50 51
51 /* Register interrupt */ 52 setup_irq(GT641XX_TIMER0_IRQ, irq);
52 setup_irq(COBALT_GALILEO_IRQ, irq);
53
54 /* Enable interrupt */
55 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
56} 53}
57 54
58/* 55/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 13:14:11 -0500