aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/cavium-octeon
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/cavium-octeon')
-rw-r--r--arch/mips/cavium-octeon/Makefile4
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c164
-rw-r--r--arch/mips/cavium-octeon/setup.c103
3 files changed, 166 insertions, 105 deletions
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index d6903c3f3d51..139436280520 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -6,10 +6,10 @@
6# License. See the file "COPYING" in the main directory of this archive 6# License. See the file "COPYING" in the main directory of this archive
7# for more details. 7# for more details.
8# 8#
9# Copyright (C) 2005-2008 Cavium Networks 9# Copyright (C) 2005-2009 Cavium Networks
10# 10#
11 11
12obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o 12obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
13obj-y += dma-octeon.o flash_setup.o 13obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o 14obj-y += octeon-memcpy.o
15 15
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
new file mode 100644
index 000000000000..be711dd2d918
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -0,0 +1,164 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2009 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
8 */
9
10#include <linux/init.h>
11#include <linux/irq.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14
15#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-rnm-defs.h>
17
18static struct octeon_cf_data octeon_cf_data;
19
20static int __init octeon_cf_device_init(void)
21{
22 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
23 unsigned long base_ptr, region_base, region_size;
24 struct platform_device *pd;
25 struct resource cf_resources[3];
26 unsigned int num_resources;
27 int i;
28 int ret = 0;
29
30 /* Setup octeon-cf platform device if present. */
31 base_ptr = 0;
32 if (octeon_bootinfo->major_version == 1
33 && octeon_bootinfo->minor_version >= 1) {
34 if (octeon_bootinfo->compact_flash_common_base_addr)
35 base_ptr =
36 octeon_bootinfo->compact_flash_common_base_addr;
37 } else {
38 base_ptr = 0x1d000800;
39 }
40
41 if (!base_ptr)
42 return ret;
43
44 /* Find CS0 region. */
45 for (i = 0; i < 8; i++) {
46 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
47 region_base = mio_boot_reg_cfg.s.base << 16;
48 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
49 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
50 && base_ptr < region_base + region_size)
51 break;
52 }
53 if (i >= 7) {
54 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
55 goto out;
56 }
57 octeon_cf_data.base_region = i;
58 octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
59 octeon_cf_data.base_region_bias = base_ptr - region_base;
60 memset(cf_resources, 0, sizeof(cf_resources));
61 num_resources = 0;
62 cf_resources[num_resources].flags = IORESOURCE_MEM;
63 cf_resources[num_resources].start = region_base;
64 cf_resources[num_resources].end = region_base + region_size - 1;
65 num_resources++;
66
67
68 if (!(base_ptr & 0xfffful)) {
69 /*
70 * Boot loader signals availability of DMA (true_ide
71 * mode) by setting low order bits of base_ptr to
72 * zero.
73 */
74
75 /* Asume that CS1 immediately follows. */
76 mio_boot_reg_cfg.u64 =
77 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
78 region_base = mio_boot_reg_cfg.s.base << 16;
79 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
80 if (!mio_boot_reg_cfg.s.en)
81 goto out;
82
83 cf_resources[num_resources].flags = IORESOURCE_MEM;
84 cf_resources[num_resources].start = region_base;
85 cf_resources[num_resources].end = region_base + region_size - 1;
86 num_resources++;
87
88 octeon_cf_data.dma_engine = 0;
89 cf_resources[num_resources].flags = IORESOURCE_IRQ;
90 cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
91 cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
92 num_resources++;
93 } else {
94 octeon_cf_data.dma_engine = -1;
95 }
96
97 pd = platform_device_alloc("pata_octeon_cf", -1);
98 if (!pd) {
99 ret = -ENOMEM;
100 goto out;
101 }
102 pd->dev.platform_data = &octeon_cf_data;
103
104 ret = platform_device_add_resources(pd, cf_resources, num_resources);
105 if (ret)
106 goto fail;
107
108 ret = platform_device_add(pd);
109 if (ret)
110 goto fail;
111
112 return ret;
113fail:
114 platform_device_put(pd);
115out:
116 return ret;
117}
118device_initcall(octeon_cf_device_init);
119
120/* Octeon Random Number Generator. */
121static int __init octeon_rng_device_init(void)
122{
123 struct platform_device *pd;
124 int ret = 0;
125
126 struct resource rng_resources[] = {
127 {
128 .flags = IORESOURCE_MEM,
129 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
130 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
131 }, {
132 .flags = IORESOURCE_MEM,
133 .start = cvmx_build_io_address(8, 0),
134 .end = cvmx_build_io_address(8, 0) + 0x7
135 }
136 };
137
138 pd = platform_device_alloc("octeon_rng", -1);
139 if (!pd) {
140 ret = -ENOMEM;
141 goto out;
142 }
143
144 ret = platform_device_add_resources(pd, rng_resources,
145 ARRAY_SIZE(rng_resources));
146 if (ret)
147 goto fail;
148
149 ret = platform_device_add(pd);
150 if (ret)
151 goto fail;
152
153 return ret;
154fail:
155 platform_device_put(pd);
156
157out:
158 return ret;
159}
160device_initcall(octeon_rng_device_init);
161
162MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
163MODULE_LICENSE("GPL");
164MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index da559249cc2f..b321d3b16877 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -11,7 +11,6 @@
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/serial.h> 14#include <linux/serial.h>
16#include <linux/smp.h> 15#include <linux/smp.h>
17#include <linux/types.h> 16#include <linux/types.h>
@@ -824,105 +823,3 @@ void prom_free_prom_memory(void)
824 CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */ 823 CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
825 octeon_hal_setup_reserved32(); 824 octeon_hal_setup_reserved32();
826} 825}
827
828static struct octeon_cf_data octeon_cf_data;
829
830static int __init octeon_cf_device_init(void)
831{
832 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
833 unsigned long base_ptr, region_base, region_size;
834 struct platform_device *pd;
835 struct resource cf_resources[3];
836 unsigned int num_resources;
837 int i;
838 int ret = 0;
839
840 /* Setup octeon-cf platform device if present. */
841 base_ptr = 0;
842 if (octeon_bootinfo->major_version == 1
843 && octeon_bootinfo->minor_version >= 1) {
844 if (octeon_bootinfo->compact_flash_common_base_addr)
845 base_ptr =
846 octeon_bootinfo->compact_flash_common_base_addr;
847 } else {
848 base_ptr = 0x1d000800;
849 }
850
851 if (!base_ptr)
852 return ret;
853
854 /* Find CS0 region. */
855 for (i = 0; i < 8; i++) {
856 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
857 region_base = mio_boot_reg_cfg.s.base << 16;
858 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
859 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
860 && base_ptr < region_base + region_size)
861 break;
862 }
863 if (i >= 7) {
864 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
865 goto out;
866 }
867 octeon_cf_data.base_region = i;
868 octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
869 octeon_cf_data.base_region_bias = base_ptr - region_base;
870 memset(cf_resources, 0, sizeof(cf_resources));
871 num_resources = 0;
872 cf_resources[num_resources].flags = IORESOURCE_MEM;
873 cf_resources[num_resources].start = region_base;
874 cf_resources[num_resources].end = region_base + region_size - 1;
875 num_resources++;
876
877
878 if (!(base_ptr & 0xfffful)) {
879 /*
880 * Boot loader signals availability of DMA (true_ide
881 * mode) by setting low order bits of base_ptr to
882 * zero.
883 */
884
885 /* Asume that CS1 immediately follows. */
886 mio_boot_reg_cfg.u64 =
887 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
888 region_base = mio_boot_reg_cfg.s.base << 16;
889 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
890 if (!mio_boot_reg_cfg.s.en)
891 goto out;
892
893 cf_resources[num_resources].flags = IORESOURCE_MEM;
894 cf_resources[num_resources].start = region_base;
895 cf_resources[num_resources].end = region_base + region_size - 1;
896 num_resources++;
897
898 octeon_cf_data.dma_engine = 0;
899 cf_resources[num_resources].flags = IORESOURCE_IRQ;
900 cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
901 cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
902 num_resources++;
903 } else {
904 octeon_cf_data.dma_engine = -1;
905 }
906
907 pd = platform_device_alloc("pata_octeon_cf", -1);
908 if (!pd) {
909 ret = -ENOMEM;
910 goto out;
911 }
912 pd->dev.platform_data = &octeon_cf_data;
913
914 ret = platform_device_add_resources(pd, cf_resources, num_resources);
915 if (ret)
916 goto fail;
917
918 ret = platform_device_add(pd);
919 if (ret)
920 goto fail;
921
922 return ret;
923fail:
924 platform_device_put(pd);
925out:
926 return ret;
927}
928device_initcall(octeon_cf_device_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 02:31:53 -0500