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-rw-r--r--arch/mips/cavium-octeon/serial.c6
-rw-r--r--arch/mips/cavium-octeon/setup.c27
2 files changed, 6 insertions, 27 deletions
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
index 8240728d485a..83eac37a1ff9 100644
--- a/arch/mips/cavium-octeon/serial.c
+++ b/arch/mips/cavium-octeon/serial.c
@@ -65,7 +65,11 @@ static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
65 p->type = PORT_OCTEON; 65 p->type = PORT_OCTEON;
66 p->iotype = UPIO_MEM; 66 p->iotype = UPIO_MEM;
67 p->regshift = 3; /* I/O addresses are every 8 bytes */ 67 p->regshift = 3; /* I/O addresses are every 8 bytes */
68 p->uartclk = mips_hpt_frequency; 68 if (octeon_is_simulation())
69 /* Make simulator output fast*/
70 p->uartclk = 115200 * 16;
71 else
72 p->uartclk = mips_hpt_frequency;
69 p->serial_in = octeon_serial_in; 73 p->serial_in = octeon_serial_in;
70 p->serial_out = octeon_serial_out; 74 p->serial_out = octeon_serial_out;
71} 75}
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 9a06fa9f9f0c..d1b5ffaf0281 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -403,7 +403,6 @@ void __init prom_init(void)
403 const int coreid = cvmx_get_core_num(); 403 const int coreid = cvmx_get_core_num();
404 int i; 404 int i;
405 int argc; 405 int argc;
406 struct uart_port octeon_port;
407#ifdef CONFIG_CAVIUM_RESERVE32 406#ifdef CONFIG_CAVIUM_RESERVE32
408 int64_t addr = -1; 407 int64_t addr = -1;
409#endif 408#endif
@@ -610,30 +609,6 @@ void __init prom_init(void)
610 _machine_restart = octeon_restart; 609 _machine_restart = octeon_restart;
611 _machine_halt = octeon_halt; 610 _machine_halt = octeon_halt;
612 611
613 memset(&octeon_port, 0, sizeof(octeon_port));
614 /*
615 * For early_serial_setup we don't set the port type or
616 * UPF_FIXED_TYPE.
617 */
618 octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ;
619 octeon_port.iotype = UPIO_MEM;
620 /* I/O addresses are every 8 bytes */
621 octeon_port.regshift = 3;
622 /* Clock rate of the chip */
623 octeon_port.uartclk = mips_hpt_frequency;
624 octeon_port.fifosize = 64;
625 octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart);
626 octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase);
627 octeon_port.serial_in = octeon_serial_in;
628 octeon_port.serial_out = octeon_serial_out;
629#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
630 octeon_port.line = 0;
631#else
632 octeon_port.line = octeon_uart;
633#endif
634 octeon_port.irq = 42 + octeon_uart;
635 early_serial_setup(&octeon_port);
636
637 octeon_user_io_init(); 612 octeon_user_io_init();
638 register_smp_ops(&octeon_smp_ops); 613 register_smp_ops(&octeon_smp_ops);
639} 614}
@@ -727,7 +702,7 @@ int prom_putchar(char c)
727 } while ((lsrval & 0x20) == 0); 702 } while ((lsrval & 0x20) == 0);
728 703
729 /* Write the byte */ 704 /* Write the byte */
730 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c); 705 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
731 return 1; 706 return 1;
732} 707}
733 708