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-rw-r--r--arch/mips/cavium-octeon/setup.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 0707fae3f0ee..2d9028f1474c 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -288,7 +288,6 @@ void octeon_user_io_init(void)
288 union octeon_cvmemctl cvmmemctl; 288 union octeon_cvmemctl cvmmemctl;
289 union cvmx_iob_fau_timeout fau_timeout; 289 union cvmx_iob_fau_timeout fau_timeout;
290 union cvmx_pow_nw_tim nm_tim; 290 union cvmx_pow_nw_tim nm_tim;
291 uint64_t cvmctl;
292 291
293 /* Get the current settings for CP0_CVMMEMCTL_REG */ 292 /* Get the current settings for CP0_CVMMEMCTL_REG */
294 cvmmemctl.u64 = read_c0_cvmmemctl(); 293 cvmmemctl.u64 = read_c0_cvmmemctl();
@@ -392,12 +391,6 @@ void octeon_user_io_init(void)
392 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 391 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
393 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 392 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
394 393
395 /* Move the performance counter interrupts to IRQ 6 */
396 cvmctl = read_c0_cvmctl();
397 cvmctl &= ~(7 << 7);
398 cvmctl |= 6 << 7;
399 write_c0_cvmctl(cvmctl);
400
401 /* Set a default for the hardware timeouts */ 394 /* Set a default for the hardware timeouts */
402 fau_timeout.u64 = 0; 395 fau_timeout.u64 = 0;
403 fau_timeout.s.tout_val = 0xfff; 396 fau_timeout.s.tout_val = 0xfff;