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-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-l2c.c66
1 files changed, 33 insertions, 33 deletions
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 33b72144db31..42e38c30b540 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -147,7 +147,7 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask)
147 mask &= valid_mask; 147 mask &= valid_mask;
148 148
149 /* A UMSK setting which blocks all L2C Ways is an error on some chips */ 149 /* A UMSK setting which blocks all L2C Ways is an error on some chips */
150 if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX)) 150 if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
151 return -1; 151 return -1;
152 152
153 if (OCTEON_IS_MODEL(OCTEON_CN63XX)) 153 if (OCTEON_IS_MODEL(OCTEON_CN63XX))
@@ -438,7 +438,7 @@ void cvmx_l2c_flush(void)
438 for (set = 0; set < n_set; set++) { 438 for (set = 0; set < n_set; set++) {
439 for (assoc = 0; assoc < n_assoc; assoc++) { 439 for (assoc = 0; assoc < n_assoc; assoc++) {
440 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 440 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
441 (assoc << assoc_shift) | (set << set_shift)); 441 (assoc << assoc_shift) | (set << set_shift));
442 CVMX_CACHE_WBIL2I(address, 0); 442 CVMX_CACHE_WBIL2I(address, 0);
443 } 443 }
444 } 444 }
@@ -573,8 +573,8 @@ union __cvmx_l2c_tag {
573 * @index: Index of the cacheline 573 * @index: Index of the cacheline
574 * 574 *
575 * Returns The Octeon model specific tag structure. This is 575 * Returns The Octeon model specific tag structure. This is
576 * translated by a wrapper function to a generic form that is 576 * translated by a wrapper function to a generic form that is
577 * easier for applications to use. 577 * easier for applications to use.
578 */ 578 */
579static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index) 579static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
580{ 580{
@@ -618,12 +618,12 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
618 ".set push\n\t" 618 ".set push\n\t"
619 ".set mips64\n\t" 619 ".set mips64\n\t"
620 ".set noreorder\n\t" 620 ".set noreorder\n\t"
621 "sd %[dbg_val], 0(%[dbg_addr])\n\t" /* Enter debug mode, wait for store */ 621 "sd %[dbg_val], 0(%[dbg_addr])\n\t" /* Enter debug mode, wait for store */
622 "ld $0, 0(%[dbg_addr])\n\t" 622 "ld $0, 0(%[dbg_addr])\n\t"
623 "ld %[tag_val], 0(%[tag_addr])\n\t" /* Read L2C tag data */ 623 "ld %[tag_val], 0(%[tag_addr])\n\t" /* Read L2C tag data */
624 "sd $0, 0(%[dbg_addr])\n\t" /* Exit debug mode, wait for store */ 624 "sd $0, 0(%[dbg_addr])\n\t" /* Exit debug mode, wait for store */
625 "ld $0, 0(%[dbg_addr])\n\t" 625 "ld $0, 0(%[dbg_addr])\n\t"
626 "cache 9, 0($0)\n\t" /* Invalidate dcache to discard debug data */ 626 "cache 9, 0($0)\n\t" /* Invalidate dcache to discard debug data */
627 ".set pop" 627 ".set pop"
628 : [tag_val] "=r" (tag_val) 628 : [tag_val] "=r" (tag_val)
629 : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr) 629 : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)
@@ -664,10 +664,10 @@ union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
664 CVMX_SYNC; /* make sure CVMX_L2C_TADX_TAG is updated */ 664 CVMX_SYNC; /* make sure CVMX_L2C_TADX_TAG is updated */
665 l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0)); 665 l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
666 666
667 tag.s.V = l2c_tadx_tag.s.valid; 667 tag.s.V = l2c_tadx_tag.s.valid;
668 tag.s.D = l2c_tadx_tag.s.dirty; 668 tag.s.D = l2c_tadx_tag.s.dirty;
669 tag.s.L = l2c_tadx_tag.s.lock; 669 tag.s.L = l2c_tadx_tag.s.lock;
670 tag.s.U = l2c_tadx_tag.s.use; 670 tag.s.U = l2c_tadx_tag.s.use;
671 tag.s.addr = l2c_tadx_tag.s.tag; 671 tag.s.addr = l2c_tadx_tag.s.tag;
672 } else { 672 } else {
673 union __cvmx_l2c_tag tmp_tag; 673 union __cvmx_l2c_tag tmp_tag;
@@ -679,34 +679,34 @@ union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
679 * as it can represent all models. 679 * as it can represent all models.
680 */ 680 */
681 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) { 681 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
682 tag.s.V = tmp_tag.cn58xx.V; 682 tag.s.V = tmp_tag.cn58xx.V;
683 tag.s.D = tmp_tag.cn58xx.D; 683 tag.s.D = tmp_tag.cn58xx.D;
684 tag.s.L = tmp_tag.cn58xx.L; 684 tag.s.L = tmp_tag.cn58xx.L;
685 tag.s.U = tmp_tag.cn58xx.U; 685 tag.s.U = tmp_tag.cn58xx.U;
686 tag.s.addr = tmp_tag.cn58xx.addr; 686 tag.s.addr = tmp_tag.cn58xx.addr;
687 } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { 687 } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
688 tag.s.V = tmp_tag.cn38xx.V; 688 tag.s.V = tmp_tag.cn38xx.V;
689 tag.s.D = tmp_tag.cn38xx.D; 689 tag.s.D = tmp_tag.cn38xx.D;
690 tag.s.L = tmp_tag.cn38xx.L; 690 tag.s.L = tmp_tag.cn38xx.L;
691 tag.s.U = tmp_tag.cn38xx.U; 691 tag.s.U = tmp_tag.cn38xx.U;
692 tag.s.addr = tmp_tag.cn38xx.addr; 692 tag.s.addr = tmp_tag.cn38xx.addr;
693 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { 693 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
694 tag.s.V = tmp_tag.cn31xx.V; 694 tag.s.V = tmp_tag.cn31xx.V;
695 tag.s.D = tmp_tag.cn31xx.D; 695 tag.s.D = tmp_tag.cn31xx.D;
696 tag.s.L = tmp_tag.cn31xx.L; 696 tag.s.L = tmp_tag.cn31xx.L;
697 tag.s.U = tmp_tag.cn31xx.U; 697 tag.s.U = tmp_tag.cn31xx.U;
698 tag.s.addr = tmp_tag.cn31xx.addr; 698 tag.s.addr = tmp_tag.cn31xx.addr;
699 } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { 699 } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
700 tag.s.V = tmp_tag.cn30xx.V; 700 tag.s.V = tmp_tag.cn30xx.V;
701 tag.s.D = tmp_tag.cn30xx.D; 701 tag.s.D = tmp_tag.cn30xx.D;
702 tag.s.L = tmp_tag.cn30xx.L; 702 tag.s.L = tmp_tag.cn30xx.L;
703 tag.s.U = tmp_tag.cn30xx.U; 703 tag.s.U = tmp_tag.cn30xx.U;
704 tag.s.addr = tmp_tag.cn30xx.addr; 704 tag.s.addr = tmp_tag.cn30xx.addr;
705 } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { 705 } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
706 tag.s.V = tmp_tag.cn50xx.V; 706 tag.s.V = tmp_tag.cn50xx.V;
707 tag.s.D = tmp_tag.cn50xx.D; 707 tag.s.D = tmp_tag.cn50xx.D;
708 tag.s.L = tmp_tag.cn50xx.L; 708 tag.s.L = tmp_tag.cn50xx.L;
709 tag.s.U = tmp_tag.cn50xx.U; 709 tag.s.U = tmp_tag.cn50xx.U;
710 tag.s.addr = tmp_tag.cn50xx.addr; 710 tag.s.addr = tmp_tag.cn50xx.addr;
711 } else { 711 } else {
712 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__); 712 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
@@ -865,7 +865,7 @@ void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
865 uint64_t address; 865 uint64_t address;
866 /* Create the address based on index and association. 866 /* Create the address based on index and association.
867 * Bits<20:17> select the way of the cache block involved in 867 * Bits<20:17> select the way of the cache block involved in
868 * the operation 868 * the operation
869 * Bits<16:7> of the effect address select the index 869 * Bits<16:7> of the effect address select the index
870 */ 870 */
871 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 871 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 04:27:46 -0500