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-rw-r--r--arch/mips/cavium-octeon/crypto/octeon-crypto.h80
1 files changed, 77 insertions, 3 deletions
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.h b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
index 355072535110..7315cc307397 100644
--- a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@ -33,7 +33,7 @@ do { \
33 __asm__ __volatile__ ( \ 33 __asm__ __volatile__ ( \
34 "dmtc2 %[rt],0x0048+" STR(index) \ 34 "dmtc2 %[rt],0x0048+" STR(index) \
35 : \ 35 : \
36 : [rt] "d" (value)); \ 36 : [rt] "d" (cpu_to_be64(value))); \
37} while (0) 37} while (0)
38 38
39/* 39/*
@@ -48,7 +48,7 @@ do { \
48 : [rt] "=d" (__value) \ 48 : [rt] "=d" (__value) \
49 : ); \ 49 : ); \
50 \ 50 \
51 __value; \ 51 be64_to_cpu(__value); \
52}) 52})
53 53
54/* 54/*
@@ -59,7 +59,7 @@ do { \
59 __asm__ __volatile__ ( \ 59 __asm__ __volatile__ ( \
60 "dmtc2 %[rt],0x0040+" STR(index) \ 60 "dmtc2 %[rt],0x0040+" STR(index) \
61 : \ 61 : \
62 : [rt] "d" (value)); \ 62 : [rt] "d" (cpu_to_be64(value))); \
63} while (0) 63} while (0)
64 64
65/* 65/*
@@ -70,6 +70,80 @@ do { \
70 __asm__ __volatile__ ( \ 70 __asm__ __volatile__ ( \
71 "dmtc2 %[rt],0x4047" \ 71 "dmtc2 %[rt],0x4047" \
72 : \ 72 : \
73 : [rt] "d" (cpu_to_be64(value))); \
74} while (0)
75
76/*
77 * The value is the final block dword (64-bit).
78 */
79#define octeon_sha1_start(value) \
80do { \
81 __asm__ __volatile__ ( \
82 "dmtc2 %[rt],0x4057" \
83 : \
84 : [rt] "d" (value)); \
85} while (0)
86
87/*
88 * The value is the final block dword (64-bit).
89 */
90#define octeon_sha256_start(value) \
91do { \
92 __asm__ __volatile__ ( \
93 "dmtc2 %[rt],0x404f" \
94 : \
95 : [rt] "d" (value)); \
96} while (0)
97
98/*
99 * Macros needed to implement SHA512:
100 */
101
102/*
103 * The index can be 0-7.
104 */
105#define write_octeon_64bit_hash_sha512(value, index) \
106do { \
107 __asm__ __volatile__ ( \
108 "dmtc2 %[rt],0x0250+" STR(index) \
109 : \
110 : [rt] "d" (value)); \
111} while (0)
112
113/*
114 * The index can be 0-7.
115 */
116#define read_octeon_64bit_hash_sha512(index) \
117({ \
118 u64 __value; \
119 \
120 __asm__ __volatile__ ( \
121 "dmfc2 %[rt],0x0250+" STR(index) \
122 : [rt] "=d" (__value) \
123 : ); \
124 \
125 __value; \
126})
127
128/*
129 * The index can be 0-14.
130 */
131#define write_octeon_64bit_block_sha512(value, index) \
132do { \
133 __asm__ __volatile__ ( \
134 "dmtc2 %[rt],0x0240+" STR(index) \
135 : \
136 : [rt] "d" (value)); \
137} while (0)
138
139/*
140 * The value is the final block word (64-bit).
141 */
142#define octeon_sha512_start(value) \
143do { \
144 __asm__ __volatile__ ( \
145 "dmtc2 %[rt],0x424f" \
146 : \
73 : [rt] "d" (value)); \ 147 : [rt] "d" (value)); \
74} while (0) 148} while (0)
75 149