1 files changed, 0 insertions, 109 deletions
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 1525f8a3841b..30c6803b5403 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -26,114 +26,6 @@ static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
 static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
 static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
-#ifndef BCMCPU_RUNTIME_DETECT
-#ifdef CONFIG_BCM63XX_CPU_3368
-#define irq_stat_reg            PERF_IRQSTAT_3368_REG
-#define irq_mask_reg            PERF_IRQMASK_3368_REG
-#define irq_bits                32
-#define is_ext_irq_cascaded     0
-#define ext_irq_start           0
-#define ext_irq_end             0
-#define ext_irq_count           4
-#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_3368
-#define ext_irq_cfg_reg2        0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6328
-#define irq_stat_reg            PERF_IRQSTAT_6328_REG
-#define irq_mask_reg            PERF_IRQMASK_6328_REG
-#define irq_bits                64
-#define is_ext_irq_cascaded     1
-#define ext_irq_start           (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end             (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
-#define ext_irq_count           4
-#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6328
-#define ext_irq_cfg_reg2        0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6338
-#define irq_stat_reg            PERF_IRQSTAT_6338_REG
-#define irq_mask_reg            PERF_IRQMASK_6338_REG
-#define irq_bits                32
-#define is_ext_irq_cascaded     0
-#define ext_irq_start           0
-#define ext_irq_end             0
-#define ext_irq_count           4
-#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6338
-#define ext_irq_cfg_reg2        0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6345
-#define irq_stat_reg            PERF_IRQSTAT_6345_REG
-#define irq_mask_reg            PERF_IRQMASK_6345_REG
-#define irq_bits                32
-#define is_ext_irq_cascaded     0
-#define ext_irq_start           0
-#define ext_irq_end             0
-#define ext_irq_count           4
-#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6345
-#define ext_irq_cfg_reg2        0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6348
-#define irq_stat_reg            PERF_IRQSTAT_6348_REG
-#define irq_mask_reg            PERF_IRQMASK_6348_REG
-#define irq_bits                32
-#define is_ext_irq_cascaded     0
-#define ext_irq_start           0
-#define ext_irq_end             0
-#define ext_irq_count           4
-#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6348
-#define ext_irq_cfg_reg2        0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6358
-#define irq_stat_reg            PERF_IRQSTAT_6358_REG
-#define irq_mask_reg            PERF_IRQMASK_6358_REG
-#define irq_bits                32
-#define is_ext_irq_cascaded     1
-#define ext_irq_start           (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end             (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
-#define ext_irq_count           4
-#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6358
-#define ext_irq_cfg_reg2        0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6362
-#define irq_stat_reg            PERF_IRQSTAT_6362_REG
-#define irq_mask_reg            PERF_IRQMASK_6362_REG
-#define irq_bits                64
-#define is_ext_irq_cascaded     1
-#define ext_irq_start           (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end             (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
-#define ext_irq_count           4
-#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6362
-#define ext_irq_cfg_reg2        0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6368
-#define irq_stat_reg            PERF_IRQSTAT_6368_REG
-#define irq_mask_reg            PERF_IRQMASK_6368_REG
-#define irq_bits                64
-#define is_ext_irq_cascaded     1
-#define ext_irq_start           (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end             (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
-#define ext_irq_count           6
-#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6368
-#define ext_irq_cfg_reg2        PERF_EXTIRQ_CFG_REG2_6368
-#endif
-#if irq_bits == 32
-#define dispatch_internal                       __dispatch_internal
-#define internal_irq_mask                       __internal_irq_mask_32
-#define internal_irq_unmask                     __internal_irq_unmask_32
-#else
-#define dispatch_internal                       __dispatch_internal_64
-#define internal_irq_mask                       __internal_irq_mask_64
-#define internal_irq_unmask                     __internal_irq_unmask_64
-#endif
-#define irq_stat_addr   (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
-#define irq_mask_addr   (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
-static inline void bcm63xx_init_irq(void)
-{
-}
-#else /* ! BCMCPU_RUNTIME_DETECT */
 static u32 irq_stat_addr, irq_mask_addr;
 static void (*dispatch_internal)(void);
 static int is_ext_irq_cascaded;
@@ -234,7 +126,6 @@ static void bcm63xx_init_irq(void)
                internal_irq_unmask = __internal_irq_unmask_64;
        }
 }
-#endif /* ! BCMCPU_RUNTIME_DETECT */
 static inline u32 get_ext_irq_perf_reg(int irq)
 {

diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 1525f8a3841b..30c6803b5403 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c
@@ -26,114 +26,6 @@ static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
26	static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;	26	static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
27	static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;	27	static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
28		28
29	#ifndef BCMCPU_RUNTIME_DETECT
30	#ifdef CONFIG_BCM63XX_CPU_3368
31	#define irq_stat_reg PERF_IRQSTAT_3368_REG
32	#define irq_mask_reg PERF_IRQMASK_3368_REG
33	#define irq_bits 32
34	#define is_ext_irq_cascaded 0
35	#define ext_irq_start 0
36	#define ext_irq_end 0
37	#define ext_irq_count 4
38	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368
39	#define ext_irq_cfg_reg2 0
40	#endif
41	#ifdef CONFIG_BCM63XX_CPU_6328
42	#define irq_stat_reg PERF_IRQSTAT_6328_REG
43	#define irq_mask_reg PERF_IRQMASK_6328_REG
44	#define irq_bits 64
45	#define is_ext_irq_cascaded 1
46	#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
47	#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
48	#define ext_irq_count 4
49	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328
50	#define ext_irq_cfg_reg2 0
51	#endif
52	#ifdef CONFIG_BCM63XX_CPU_6338
53	#define irq_stat_reg PERF_IRQSTAT_6338_REG
54	#define irq_mask_reg PERF_IRQMASK_6338_REG
55	#define irq_bits 32
56	#define is_ext_irq_cascaded 0
57	#define ext_irq_start 0
58	#define ext_irq_end 0
59	#define ext_irq_count 4
60	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338
61	#define ext_irq_cfg_reg2 0
62	#endif
63	#ifdef CONFIG_BCM63XX_CPU_6345
64	#define irq_stat_reg PERF_IRQSTAT_6345_REG
65	#define irq_mask_reg PERF_IRQMASK_6345_REG
66	#define irq_bits 32
67	#define is_ext_irq_cascaded 0
68	#define ext_irq_start 0
69	#define ext_irq_end 0
70	#define ext_irq_count 4
71	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345
72	#define ext_irq_cfg_reg2 0
73	#endif
74	#ifdef CONFIG_BCM63XX_CPU_6348
75	#define irq_stat_reg PERF_IRQSTAT_6348_REG
76	#define irq_mask_reg PERF_IRQMASK_6348_REG
77	#define irq_bits 32
78	#define is_ext_irq_cascaded 0
79	#define ext_irq_start 0
80	#define ext_irq_end 0
81	#define ext_irq_count 4
82	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348
83	#define ext_irq_cfg_reg2 0
84	#endif
85	#ifdef CONFIG_BCM63XX_CPU_6358
86	#define irq_stat_reg PERF_IRQSTAT_6358_REG
87	#define irq_mask_reg PERF_IRQMASK_6358_REG
88	#define irq_bits 32
89	#define is_ext_irq_cascaded 1
90	#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
91	#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
92	#define ext_irq_count 4
93	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
94	#define ext_irq_cfg_reg2 0
95	#endif
96	#ifdef CONFIG_BCM63XX_CPU_6362
97	#define irq_stat_reg PERF_IRQSTAT_6362_REG
98	#define irq_mask_reg PERF_IRQMASK_6362_REG
99	#define irq_bits 64
100	#define is_ext_irq_cascaded 1
101	#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
102	#define ext_irq_end (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
103	#define ext_irq_count 4
104	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6362
105	#define ext_irq_cfg_reg2 0
106	#endif
107	#ifdef CONFIG_BCM63XX_CPU_6368
108	#define irq_stat_reg PERF_IRQSTAT_6368_REG
109	#define irq_mask_reg PERF_IRQMASK_6368_REG
110	#define irq_bits 64
111	#define is_ext_irq_cascaded 1
112	#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
113	#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
114	#define ext_irq_count 6
115	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
116	#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
117	#endif
118
119	#if irq_bits == 32
120	#define dispatch_internal __dispatch_internal
121	#define internal_irq_mask __internal_irq_mask_32
122	#define internal_irq_unmask __internal_irq_unmask_32
123	#else
124	#define dispatch_internal __dispatch_internal_64
125	#define internal_irq_mask __internal_irq_mask_64
126	#define internal_irq_unmask __internal_irq_unmask_64
127	#endif
128
129	#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
130	#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
131
132	static inline void bcm63xx_init_irq(void)
133	{
134	}
135	#else /* ! BCMCPU_RUNTIME_DETECT */
136
137	static u32 irq_stat_addr, irq_mask_addr;	29	static u32 irq_stat_addr, irq_mask_addr;
138	static void (*dispatch_internal)(void);	30	static void (*dispatch_internal)(void);
139	static int is_ext_irq_cascaded;	31	static int is_ext_irq_cascaded;
@@ -234,7 +126,6 @@ static void bcm63xx_init_irq(void)
234	internal_irq_unmask = __internal_irq_unmask_64;	126	internal_irq_unmask = __internal_irq_unmask_64;
235	}	127	}
236	}	128	}
237	#endif /* ! BCMCPU_RUNTIME_DETECT */
238		129
239	static inline u32 get_ext_irq_perf_reg(int irq)	130	static inline u32 get_ext_irq_perf_reg(int irq)
240	{	131	{