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-rw-r--r--arch/mips/bcm63xx/reset.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/mips/bcm63xx/reset.c b/arch/mips/bcm63xx/reset.c
index 68a31bb90cbf..317931c6cf58 100644
--- a/arch/mips/bcm63xx/reset.c
+++ b/arch/mips/bcm63xx/reset.c
@@ -85,6 +85,20 @@
85#define BCM6358_RESET_PCIE 0 85#define BCM6358_RESET_PCIE 0
86#define BCM6358_RESET_PCIE_EXT 0 86#define BCM6358_RESET_PCIE_EXT 0
87 87
88#define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK
89#define BCM6362_RESET_ENET 0
90#define BCM6362_RESET_USBH SOFTRESET_6362_USBH_MASK
91#define BCM6362_RESET_USBD SOFTRESET_6362_USBS_MASK
92#define BCM6362_RESET_DSL 0
93#define BCM6362_RESET_SAR SOFTRESET_6362_SAR_MASK
94#define BCM6362_RESET_EPHY SOFTRESET_6362_EPHY_MASK
95#define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK
96#define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK
97#define BCM6362_RESET_MPI 0
98#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \
99 SOFTRESET_6362_PCIE_CORE_MASK)
100#define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK
101
88#define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK 102#define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
89#define BCM6368_RESET_ENET 0 103#define BCM6368_RESET_ENET 0
90#define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK 104#define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK
@@ -119,6 +133,10 @@ static const u32 bcm6358_reset_bits[] = {
119 __GEN_RESET_BITS_TABLE(6358) 133 __GEN_RESET_BITS_TABLE(6358)
120}; 134};
121 135
136static const u32 bcm6362_reset_bits[] = {
137 __GEN_RESET_BITS_TABLE(6362)
138};
139
122static const u32 bcm6368_reset_bits[] = { 140static const u32 bcm6368_reset_bits[] = {
123 __GEN_RESET_BITS_TABLE(6368) 141 __GEN_RESET_BITS_TABLE(6368)
124}; 142};
@@ -140,6 +158,9 @@ static int __init bcm63xx_reset_bits_init(void)
140 } else if (BCMCPU_IS_6358()) { 158 } else if (BCMCPU_IS_6358()) {
141 reset_reg = PERF_SOFTRESET_6358_REG; 159 reset_reg = PERF_SOFTRESET_6358_REG;
142 bcm63xx_reset_bits = bcm6358_reset_bits; 160 bcm63xx_reset_bits = bcm6358_reset_bits;
161 } else if (BCMCPU_IS_6362()) {
162 reset_reg = PERF_SOFTRESET_6362_REG;
163 bcm63xx_reset_bits = bcm6362_reset_bits;
143 } else if (BCMCPU_IS_6368()) { 164 } else if (BCMCPU_IS_6368()) {
144 reset_reg = PERF_SOFTRESET_6368_REG; 165 reset_reg = PERF_SOFTRESET_6368_REG;
145 bcm63xx_reset_bits = bcm6368_reset_bits; 166 bcm63xx_reset_bits = bcm6368_reset_bits;
@@ -182,6 +203,13 @@ static const u32 bcm63xx_reset_bits[] = {
182#define reset_reg PERF_SOFTRESET_6358_REG 203#define reset_reg PERF_SOFTRESET_6358_REG
183#endif 204#endif
184 205
206#ifdef CONFIG_BCM63XX_CPU_6362
207static const u32 bcm63xx_reset_bits[] = {
208 __GEN_RESET_BITS_TABLE(6362)
209};
210#define reset_reg PERF_SOFTRESET_6362_REG
211#endif
212
185#ifdef CONFIG_BCM63XX_CPU_6368 213#ifdef CONFIG_BCM63XX_CPU_6368
186static const u32 bcm63xx_reset_bits[] = { 214static const u32 bcm63xx_reset_bits[] = {
187 __GEN_RESET_BITS_TABLE(6368) 215 __GEN_RESET_BITS_TABLE(6368)