1 files changed, 67 insertions, 3 deletions

diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 2c68ee9ccee2..9d57c71b7b58 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -10,6 +10,7 @@
 #include <linux/mutex.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
@@ -113,6 +114,34 @@ static struct clk clk_ephy = {
 };
 
 /*
+ * Ethernet switch clock
+ */
+static void enetsw_set(struct clk *clk, int enable)
+{
+        if (!BCMCPU_IS_6368())
+                return;
+        bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
+                        CKCTL_6368_SWPKT_USB_EN |
+                        CKCTL_6368_SWPKT_SAR_EN, enable);
+        if (enable) {
+                u32 val;
+
+                /* reset switch core afer clock change */
+                val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
+                val &= ~SOFTRESET_6368_ENETSW_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                msleep(10);
+                val |= SOFTRESET_6368_ENETSW_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                msleep(10);
+        }
+}
+
+static struct clk clk_enetsw = {
+        .set    = enetsw_set,
+};
+
+/*
  * PCM clock
  */
 static void pcm_set(struct clk *clk, int enable)
@@ -131,9 +160,10 @@ static struct clk clk_pcm = {
  */
 static void usbh_set(struct clk *clk, int enable)
 {
-        if (!BCMCPU_IS_6348())
-                return;
-        bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+        if (BCMCPU_IS_6348())
+                bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+        else if (BCMCPU_IS_6368())
+                bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
 }
 
 static struct clk clk_usbh = {
@@ -162,6 +192,36 @@ static struct clk clk_spi = {
 };
 
 /*
+ * XTM clock
+ */
+static void xtm_set(struct clk *clk, int enable)
+{
+        if (!BCMCPU_IS_6368())
+                return;
+
+        bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
+                        CKCTL_6368_SWPKT_SAR_EN, enable);
+
+        if (enable) {
+                u32 val;
+
+                /* reset sar core afer clock change */
+                val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
+                val &= ~SOFTRESET_6368_SAR_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                mdelay(1);
+                val |= SOFTRESET_6368_SAR_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                mdelay(1);
+        }
+}
+
+
+static struct clk clk_xtm = {
+        .set    = xtm_set,
+};
+
+/*
  * Internal peripheral clock
  */
 static struct clk clk_periph = {
@@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
                 return &clk_enet0;
         if (!strcmp(id, "enet1"))
                 return &clk_enet1;
+        if (!strcmp(id, "enetsw"))
+                return &clk_enetsw;
         if (!strcmp(id, "ephy"))
                 return &clk_ephy;
         if (!strcmp(id, "usbh"))
                 return &clk_usbh;
         if (!strcmp(id, "spi"))
                 return &clk_spi;
+        if (!strcmp(id, "xtm"))
+                return &clk_xtm;
         if (!strcmp(id, "periph"))
                 return &clk_periph;
         if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))