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-rw-r--r--arch/mips/basler/excite/Kconfig9
-rw-r--r--arch/mips/basler/excite/Makefile8
-rw-r--r--arch/mips/basler/excite/excite_device.c403
-rw-r--r--arch/mips/basler/excite/excite_iodev.c178
-rw-r--r--arch/mips/basler/excite/excite_iodev.h10
-rw-r--r--arch/mips/basler/excite/excite_irq.c122
-rw-r--r--arch/mips/basler/excite/excite_procfs.c92
-rw-r--r--arch/mips/basler/excite/excite_prom.c144
-rw-r--r--arch/mips/basler/excite/excite_setup.c302
9 files changed, 0 insertions, 1268 deletions
diff --git a/arch/mips/basler/excite/Kconfig b/arch/mips/basler/excite/Kconfig
deleted file mode 100644
index ba506075608b..000000000000
--- a/arch/mips/basler/excite/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
1config BASLER_EXCITE_PROTOTYPE
2 bool "Support for pre-release units"
3 depends on BASLER_EXCITE
4 default n
5 help
6 Pre-series (prototype) units are different from later ones in
7 some ways. Select this option if you have one of these. Please
8 note that a kernel built with this option selected will not be
9 able to run on normal units.
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
deleted file mode 100644
index cff29cf46d03..000000000000
--- a/arch/mips/basler/excite/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for Basler eXcite
3#
4
5obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
6 excite_device.o excite_procfs.o
7
8obj-m += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
deleted file mode 100644
index e00bc2d7f301..000000000000
--- a/arch/mips/basler/excite/excite_device.c
+++ /dev/null
@@ -1,403 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/ioport.h>
24#include <linux/err.h>
25#include <linux/jiffies.h>
26#include <linux/sched.h>
27#include <asm/types.h>
28#include <asm/rm9k-ocd.h>
29
30#include <excite.h>
31#include <rm9k_eth.h>
32#include <rm9k_wdt.h>
33#include <rm9k_xicap.h>
34#include <excite_nandflash.h>
35
36#include "excite_iodev.h"
37
38#define RM9K_GE_UNIT 0
39#define XICAP_UNIT 0
40#define NAND_UNIT 0
41
42#define DLL_TIMEOUT 3 /* seconds */
43
44
45#define RINIT(__start__, __end__, __name__, __parent__) { \
46 .name = __name__ "_0", \
47 .start = (__start__), \
48 .end = (__end__), \
49 .flags = 0, \
50 .parent = (__parent__) \
51}
52
53#define RINIT_IRQ(__irq__, __name__) { \
54 .name = __name__ "_0", \
55 .start = (__irq__), \
56 .end = (__irq__), \
57 .flags = IORESOURCE_IRQ, \
58 .parent = NULL \
59}
60
61
62
63enum {
64 slice_xicap,
65 slice_eth
66};
67
68
69
70static struct resource
71 excite_ctr_resource __maybe_unused = {
72 .name = "GPI counters",
73 .start = 0,
74 .end = 5,
75 .flags = 0,
76 .parent = NULL,
77 .sibling = NULL,
78 .child = NULL
79 },
80 excite_gpislice_resource __maybe_unused = {
81 .name = "GPI slices",
82 .start = 0,
83 .end = 1,
84 .flags = 0,
85 .parent = NULL,
86 .sibling = NULL,
87 .child = NULL
88 },
89 excite_mdio_channel_resource __maybe_unused = {
90 .name = "MDIO channels",
91 .start = 0,
92 .end = 1,
93 .flags = 0,
94 .parent = NULL,
95 .sibling = NULL,
96 .child = NULL
97 },
98 excite_fifomem_resource __maybe_unused = {
99 .name = "FIFO memory",
100 .start = 0,
101 .end = 767,
102 .flags = 0,
103 .parent = NULL,
104 .sibling = NULL,
105 .child = NULL
106 },
107 excite_scram_resource __maybe_unused = {
108 .name = "Scratch RAM",
109 .start = EXCITE_PHYS_SCRAM,
110 .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
111 .flags = IORESOURCE_MEM,
112 .parent = NULL,
113 .sibling = NULL,
114 .child = NULL
115 },
116 excite_fpga_resource __maybe_unused = {
117 .name = "System FPGA",
118 .start = EXCITE_PHYS_FPGA,
119 .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
120 .flags = IORESOURCE_MEM,
121 .parent = NULL,
122 .sibling = NULL,
123 .child = NULL
124 },
125 excite_nand_resource __maybe_unused = {
126 .name = "NAND flash control",
127 .start = EXCITE_PHYS_NAND,
128 .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
129 .flags = IORESOURCE_MEM,
130 .parent = NULL,
131 .sibling = NULL,
132 .child = NULL
133 },
134 excite_titan_resource __maybe_unused = {
135 .name = "TITAN registers",
136 .start = EXCITE_PHYS_TITAN,
137 .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
138 .flags = IORESOURCE_MEM,
139 .parent = NULL,
140 .sibling = NULL,
141 .child = NULL
142 };
143
144
145
146static void adjust_resources(struct resource *res, unsigned int n)
147{
148 struct resource *p;
149 const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
150 | IORESOURCE_IRQ | IORESOURCE_DMA;
151
152 for (p = res; p < res + n; p++) {
153 const struct resource * const parent = p->parent;
154 if (parent) {
155 p->start += parent->start;
156 p->end += parent->start;
157 p->flags = parent->flags & mask;
158 }
159 }
160}
161
162
163
164#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
165static struct resource xicap_rsrc[] = {
166 RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
167 RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
168 RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
169 RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
170 RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
171 RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
172 RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
173 RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
174 RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
175};
176
177static struct platform_device xicap_pdev = {
178 .name = XICAP_NAME,
179 .id = XICAP_UNIT,
180 .num_resources = ARRAY_SIZE(xicap_rsrc),
181 .resource = xicap_rsrc
182};
183
184/*
185 * Create a platform device for the GPI port that receives the
186 * image data from the embedded camera.
187 */
188static int __init xicap_devinit(void)
189{
190 unsigned long tend;
191 u32 reg;
192 int retval;
193
194 adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
195
196 /* Power up the slice and configure it. */
197 reg = titan_readl(CPTC1R);
198 reg &= ~(0x11100 << slice_xicap);
199 titan_writel(reg, CPTC1R);
200
201 /* Enable slice & DLL. */
202 reg= titan_readl(CPRR);
203 reg &= ~(0x00030003 << (slice_xicap * 2));
204 titan_writel(reg, CPRR);
205
206 /* Wait for DLLs to lock */
207 tend = jiffies + DLL_TIMEOUT * HZ;
208 while (time_before(jiffies, tend)) {
209 if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
210 break;
211 yield();
212 }
213
214 if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
215 printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
216 xicap_pdev.name, DLL_TIMEOUT);
217 retval = -ETIME;
218 } else {
219 /* Register platform device */
220 retval = platform_device_register(&xicap_pdev);
221 }
222
223 return retval;
224}
225
226device_initcall(xicap_devinit);
227#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
228
229
230
231#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
232static struct resource wdt_rsrc[] = {
233 RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
234 RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
235 RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
236};
237
238static struct platform_device wdt_pdev = {
239 .name = WDT_NAME,
240 .id = -1,
241 .num_resources = ARRAY_SIZE(wdt_rsrc),
242 .resource = wdt_rsrc
243};
244
245/*
246 * Create a platform device for the GPI port that receives the
247 * image data from the embedded camera.
248 */
249static int __init wdt_devinit(void)
250{
251 adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
252 return platform_device_register(&wdt_pdev);
253}
254
255device_initcall(wdt_devinit);
256#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
257
258
259
260static struct resource excite_nandflash_rsrc[] = {
261 RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
262};
263
264static struct platform_device excite_nandflash_pdev = {
265 .name = "excite_nand",
266 .id = NAND_UNIT,
267 .num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
268 .resource = excite_nandflash_rsrc
269};
270
271/*
272 * Create a platform device for the access to the nand-flash
273 * port
274 */
275static int __init excite_nandflash_devinit(void)
276{
277 adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
278
279 /* nothing to be done here */
280
281 /* Register platform device */
282 return platform_device_register(&excite_nandflash_pdev);
283}
284
285device_initcall(excite_nandflash_devinit);
286
287
288
289static struct resource iodev_rsrc[] = {
290 RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
291};
292
293static struct platform_device io_pdev = {
294 .name = IODEV_NAME,
295 .id = -1,
296 .num_resources = ARRAY_SIZE(iodev_rsrc),
297 .resource = iodev_rsrc
298};
299
300/*
301 * Create a platform device for the external I/O ports.
302 */
303static int __init io_devinit(void)
304{
305 adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
306 return platform_device_register(&io_pdev);
307}
308
309device_initcall(io_devinit);
310
311
312
313
314#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
315static struct resource rm9k_ge_rsrc[] = {
316 RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
317 RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
318 RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
319 RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
320 RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
321 RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
322 RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
323 RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
324 RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
325 RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
326 RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
327 RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
328 RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
329 RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
330 RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
331};
332
333static struct platform_device rm9k_ge_pdev = {
334 .name = RM9K_GE_NAME,
335 .id = RM9K_GE_UNIT,
336 .num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
337 .resource = rm9k_ge_rsrc
338};
339
340
341
342/*
343 * Create a platform device for the Ethernet port.
344 */
345static int __init rm9k_ge_devinit(void)
346{
347 u32 reg;
348
349 adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
350
351 /* Power up the slice and configure it. */
352 reg = titan_readl(CPTC1R);
353 reg &= ~(0x11000 << slice_eth);
354 reg |= 0x100 << slice_eth;
355 titan_writel(reg, CPTC1R);
356
357 /* Take the MAC out of reset, reset the DLLs. */
358 reg = titan_readl(CPRR);
359 reg &= ~(0x00030000 << (slice_eth * 2));
360 reg |= 0x3 << (slice_eth * 2);
361 titan_writel(reg, CPRR);
362
363 return platform_device_register(&rm9k_ge_pdev);
364}
365
366device_initcall(rm9k_ge_devinit);
367#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
368
369
370
371static int __init excite_setup_devs(void)
372{
373 int res;
374 u32 reg;
375
376 /* Enable xdma and fifo interrupts */
377 reg = titan_readl(0x0050);
378 titan_writel(reg | 0x18000000, 0x0050);
379
380 res = request_resource(&iomem_resource, &excite_titan_resource);
381 if (res)
382 return res;
383 res = request_resource(&iomem_resource, &excite_scram_resource);
384 if (res)
385 return res;
386 res = request_resource(&iomem_resource, &excite_fpga_resource);
387 if (res)
388 return res;
389 res = request_resource(&iomem_resource, &excite_nand_resource);
390 if (res)
391 return res;
392 excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
393 ( IORESOURCE_IO | IORESOURCE_MEM
394 | IORESOURCE_IRQ | IORESOURCE_DMA);
395 excite_nand_resource.flags = excite_nand_resource.parent->flags &
396 ( IORESOURCE_IO | IORESOURCE_MEM
397 | IORESOURCE_IRQ | IORESOURCE_DMA);
398
399 return 0;
400}
401
402arch_initcall(excite_setup_devs);
403
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
deleted file mode 100644
index 938b1d0b7652..000000000000
--- a/arch/mips/basler/excite/excite_iodev.c
+++ /dev/null
@@ -1,178 +0,0 @@
1/*
2 * Copyright (C) 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/compiler.h>
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/wait.h>
25#include <linux/poll.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/miscdevice.h>
29#include <linux/smp_lock.h>
30
31#include "excite_iodev.h"
32
33
34
35static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
36static int __init iodev_probe(struct platform_device *);
37static int __exit iodev_remove(struct platform_device *);
38static int iodev_open(struct inode *, struct file *);
39static int iodev_release(struct inode *, struct file *);
40static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
41static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
42static irqreturn_t iodev_irqhdl(int, void *);
43
44
45
46static const char iodev_name[] = "iodev";
47static unsigned int iodev_irq;
48static DECLARE_WAIT_QUEUE_HEAD(wq);
49
50
51
52static const struct file_operations fops =
53{
54 .owner = THIS_MODULE,
55 .open = iodev_open,
56 .release = iodev_release,
57 .read = iodev_read,
58 .poll = iodev_poll
59};
60
61static struct miscdevice miscdev =
62{
63 .minor = MISC_DYNAMIC_MINOR,
64 .name = iodev_name,
65 .fops = &fops
66};
67
68static struct platform_driver iodev_driver = {
69 .driver = {
70 .name = iodev_name,
71 .owner = THIS_MODULE,
72 },
73 .probe = iodev_probe,
74 .remove = __devexit_p(iodev_remove),
75};
76
77
78
79static const struct resource *
80iodev_get_resource(struct platform_device *pdv, const char *name,
81 unsigned int type)
82{
83 char buf[80];
84 if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
85 return NULL;
86 return platform_get_resource_byname(pdv, type, buf);
87}
88
89
90
91/* No hotplugging on the platform bus - use __init */
92static int __init iodev_probe(struct platform_device *dev)
93{
94 const struct resource * const ri =
95 iodev_get_resource(dev, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
96
97 if (unlikely(!ri))
98 return -ENXIO;
99
100 iodev_irq = ri->start;
101 return misc_register(&miscdev);
102}
103
104
105
106static int __exit iodev_remove(struct platform_device *dev)
107{
108 return misc_deregister(&miscdev);
109}
110
111static int iodev_open(struct inode *i, struct file *f)
112{
113 int ret;
114
115 ret = request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
116 iodev_name, &miscdev);
117
118 return ret;
119}
120
121static int iodev_release(struct inode *i, struct file *f)
122{
123 free_irq(iodev_irq, &miscdev);
124 return 0;
125}
126
127
128
129
130static ssize_t
131iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
132{
133 ssize_t ret;
134 DEFINE_WAIT(w);
135
136 prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
137 if (!signal_pending(current))
138 schedule();
139 ret = signal_pending(current) ? -ERESTARTSYS : 0;
140 finish_wait(&wq, &w);
141 return ret;
142}
143
144
145static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
146{
147 poll_wait(f, &wq, p);
148 return POLLOUT | POLLWRNORM;
149}
150
151static irqreturn_t iodev_irqhdl(int irq, void *ctxt)
152{
153 wake_up(&wq);
154
155 return IRQ_HANDLED;
156}
157
158static int __init iodev_init_module(void)
159{
160 return platform_driver_register(&iodev_driver);
161}
162
163
164
165static void __exit iodev_cleanup_module(void)
166{
167 platform_driver_unregister(&iodev_driver);
168}
169
170module_init(iodev_init_module);
171module_exit(iodev_cleanup_module);
172
173
174
175MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
176MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
177MODULE_VERSION("0.0");
178MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_iodev.h b/arch/mips/basler/excite/excite_iodev.h
deleted file mode 100644
index cbfbb5d2ee62..000000000000
--- a/arch/mips/basler/excite/excite_iodev.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef __EXCITE_IODEV_H__
2#define __EXCITE_IODEV_H__
3
4/* Device name */
5#define IODEV_NAME "iodev"
6
7/* Resource names */
8#define IODEV_RESOURCE_IRQ "excite_iodev_irq"
9
10#endif /* __EXCITE_IODEV_H__ */
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
deleted file mode 100644
index 934e0a6b1011..000000000000
--- a/arch/mips/basler/excite/excite_irq.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * Copyright (C) by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslereb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/kernel_stat.h>
23#include <linux/module.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/types.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/timex.h>
30#include <linux/slab.h>
31#include <linux/random.h>
32#include <linux/bitops.h>
33#include <asm/bootinfo.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/irq_cpu.h>
37#include <asm/mipsregs.h>
38#include <asm/system.h>
39#include <asm/rm9k-ocd.h>
40
41#include <excite.h>
42
43extern asmlinkage void excite_handle_int(void);
44
45/*
46 * Initialize the interrupt handler
47 */
48void __init arch_init_irq(void)
49{
50 mips_cpu_irq_init();
51 rm7k_cpu_irq_init();
52 rm9k_cpu_irq_init();
53}
54
55asmlinkage void plat_irq_dispatch(void)
56{
57 const u32
58 interrupts = read_c0_cause() >> 8,
59 mask = ((read_c0_status() >> 8) & 0x000000ff) |
60 (read_c0_intcontrol() & 0x0000ff00),
61 pending = interrupts & mask;
62 u32 msgintflags, msgintmask, msgint;
63
64 /* process timer interrupt */
65 if (pending & (1 << TIMER_IRQ)) {
66 do_IRQ(TIMER_IRQ);
67 return;
68 }
69
70 /* Process PCI interrupts */
71#if USB_IRQ < 10
72 msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
73 msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
74 msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
75 if ((pending & (1 << USB_IRQ)) && msgint) {
76#else
77 if (pending & (1 << USB_IRQ)) {
78#endif
79 do_IRQ(USB_IRQ);
80 return;
81 }
82
83 /* Process TITAN interrupts */
84 msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
85 msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
86 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
87 if ((pending & (1 << TITAN_IRQ)) && msgint) {
88 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
89 do_IRQ(TITAN_IRQ);
90 return;
91 }
92
93 /* Process FPGA line #0 interrupts */
94 msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
95 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
96 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
97 if ((pending & (1 << FPGA0_IRQ)) && msgint) {
98 do_IRQ(FPGA0_IRQ);
99 return;
100 }
101
102 /* Process FPGA line #1 interrupts */
103 msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
104 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
105 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
106 if ((pending & (1 << FPGA1_IRQ)) && msgint) {
107 do_IRQ(FPGA1_IRQ);
108 return;
109 }
110
111 /* Process PHY interrupts */
112 msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
113 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
114 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
115 if ((pending & (1 << PHY_IRQ)) && msgint) {
116 do_IRQ(PHY_IRQ);
117 return;
118 }
119
120 /* Process spurious interrupts */
121 spurious_interrupt();
122}
diff --git a/arch/mips/basler/excite/excite_procfs.c b/arch/mips/basler/excite/excite_procfs.c
deleted file mode 100644
index 08923e6825b5..000000000000
--- a/arch/mips/basler/excite/excite_procfs.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * Procfs support for Basler eXcite
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/module.h>
22#include <linux/proc_fs.h>
23#include <linux/seq_file.h>
24#include <linux/stat.h>
25#include <asm/page.h>
26#include <asm/io.h>
27#include <asm/system.h>
28#include <asm/rm9k-ocd.h>
29
30#include <excite.h>
31
32static int excite_unit_id_proc_show(struct seq_file *m, void *v)
33{
34 seq_printf(m, "%06x", unit_id);
35 return 0;
36}
37
38static int excite_unit_id_proc_open(struct inode *inode, struct file *file)
39{
40 return single_open(file, excite_unit_id_proc_show, NULL);
41}
42
43static const struct file_operations excite_unit_id_proc_fops = {
44 .owner = THIS_MODULE,
45 .open = excite_unit_id_proc_open,
46 .read = seq_read,
47 .llseek = seq_lseek,
48 .release = single_release,
49};
50
51static int
52excite_bootrom_read(char *page, char **start, off_t off, int count,
53 int *eof, void *data)
54{
55 void __iomem * src;
56
57 if (off >= EXCITE_SIZE_BOOTROM) {
58 *eof = 1;
59 return 0;
60 }
61
62 if ((off + count) > EXCITE_SIZE_BOOTROM)
63 count = EXCITE_SIZE_BOOTROM - off;
64
65 src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
66 if (src) {
67 memcpy_fromio(page, src, count);
68 iounmap(src);
69 *start = page;
70 } else {
71 count = -ENOMEM;
72 }
73
74 return count;
75}
76
77void excite_procfs_init(void)
78{
79 /* Create & populate /proc/excite */
80 struct proc_dir_entry * const pdir = proc_mkdir("excite", NULL);
81 if (pdir) {
82 struct proc_dir_entry * e;
83
84 e = proc_create("unit_id", S_IRUGO, pdir,
85 &excite_unit_id_proc_fops);
86 if (e) e->size = 6;
87
88 e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
89 excite_bootrom_read, NULL);
90 if (e) e->size = EXCITE_SIZE_BOOTROM;
91 }
92}
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
deleted file mode 100644
index 68d8bc597e34..000000000000
--- a/arch/mips/basler/excite/excite_prom.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
3 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
4 * Manish Lachwani.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/mm.h>
24#include <linux/delay.h>
25#include <linux/smp.h>
26#include <linux/module.h>
27#include <asm/io.h>
28#include <asm/pgtable.h>
29#include <asm/processor.h>
30#include <asm/reboot.h>
31#include <asm/system.h>
32#include <asm/bootinfo.h>
33#include <asm/string.h>
34
35#include <excite.h>
36
37/* This struct is used by Redboot to pass arguments to the kernel */
38typedef struct
39{
40 char *name;
41 char *val;
42} t_env_var;
43
44struct parmblock {
45 t_env_var memsize;
46 t_env_var modetty0;
47 t_env_var ethaddr;
48 t_env_var env_end;
49 char *argv[2];
50 char text[0];
51};
52
53static unsigned int prom_argc;
54static const char ** prom_argv;
55static const t_env_var * prom_env;
56
57static void prom_halt(void) __attribute__((noreturn));
58static void prom_exit(void) __attribute__((noreturn));
59
60
61
62const char *get_system_type(void)
63{
64 return "Basler eXcite";
65}
66
67/*
68 * Halt the system
69 */
70static void prom_halt(void)
71{
72 printk(KERN_NOTICE "\n** System halted.\n");
73 while (1)
74 asm volatile (
75 "\t.set\tmips3\n"
76 "\twait\n"
77 "\t.set\tmips0\n"
78 );
79}
80
81/*
82 * Reset the CPU and re-enter Redboot
83 */
84static void prom_exit(void)
85{
86 unsigned int i;
87 volatile unsigned char * const flg =
88 (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
89
90 /* Clear the watchdog reset flag, set the reboot flag */
91 *flg &= ~0x01;
92 *flg |= 0x80;
93
94 for (i = 0; i < 10; i++) {
95 *(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
96 iob();
97 mdelay(1000);
98 }
99
100 printk(KERN_NOTICE "Reset failed\n");
101 prom_halt();
102}
103
104static const char __init *prom_getenv(char *name)
105{
106 const t_env_var * p;
107 for (p = prom_env; p->name != NULL; p++)
108 if(strcmp(name, p->name) == 0)
109 break;
110 return p->val;
111}
112
113/*
114 * Init routine which accepts the variables from Redboot
115 */
116void __init prom_init(void)
117{
118 const struct parmblock * const pb = (struct parmblock *) fw_arg2;
119
120 prom_argc = fw_arg0;
121 prom_argv = (const char **) fw_arg1;
122 prom_env = &pb->memsize;
123
124 /* Callbacks for halt, restart */
125 _machine_restart = (void (*)(char *)) prom_exit;
126 _machine_halt = prom_halt;
127
128#ifdef CONFIG_32BIT
129 /* copy command line */
130 strcpy(arcs_cmdline, prom_argv[1]);
131 memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
132 strcpy(modetty, prom_getenv("modetty0"));
133#endif /* CONFIG_32BIT */
134
135#ifdef CONFIG_64BIT
136# error 64 bit support not implemented
137#endif /* CONFIG_64BIT */
138}
139
140/* This is called from free_initmem(), so we need to provide it */
141void __init prom_free_prom_memory(void)
142{
143 /* Nothing to do */
144}
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
deleted file mode 100644
index d66b3b8edf2a..000000000000
--- a/arch/mips/basler/excite/excite_setup.c
+++ /dev/null
@@ -1,302 +0,0 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
5 * Manish Lachwani.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/tty.h>
27#include <linux/serial_core.h>
28#include <linux/serial.h>
29#include <linux/serial_8250.h>
30#include <linux/ioport.h>
31#include <linux/spinlock.h>
32#include <asm/bootinfo.h>
33#include <asm/mipsregs.h>
34#include <asm/pgtable-32.h>
35#include <asm/io.h>
36#include <asm/time.h>
37#include <asm/rm9k-ocd.h>
38
39#include <excite.h>
40
41#define TITAN_UART_CLK 25000000
42
43#if 1
44/* normal serial port assignment */
45#define REGBASE_SER0 0x0208
46#define REGBASE_SER1 0x0238
47#define MASK_SER0 0x1
48#define MASK_SER1 0x2
49#else
50/* serial ports swapped */
51#define REGBASE_SER0 0x0238
52#define REGBASE_SER1 0x0208
53#define MASK_SER0 0x2
54#define MASK_SER1 0x1
55#endif
56
57unsigned long memsize;
58char modetty[30];
59unsigned int titan_irq = TITAN_IRQ;
60static void __iomem * ctl_regs;
61u32 unit_id;
62
63volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
64volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
65
66/* Protect access to shared GPI registers */
67DEFINE_SPINLOCK(titan_lock);
68int titan_irqflags;
69
70
71/*
72 * The eXcite platform uses the alternate timer interrupt
73 *
74 * Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
75 * to handle the alternate timer interrupt of the RM9000.
76 */
77void __init plat_time_init(void)
78{
79 const u32 modebit5 = ocd_readl(0x00e4);
80 unsigned int mult = ((modebit5 >> 11) & 0x1f) + 2;
81 unsigned int div = ((modebit5 >> 16) & 0x1f) + 2;
82
83 if (div == 33)
84 div = 1;
85 mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
86}
87
88static int __init excite_init_console(void)
89{
90#if defined(CONFIG_SERIAL_8250)
91 static __initdata char serr[] =
92 KERN_ERR "Serial port #%u setup failed\n";
93 struct uart_port up;
94
95 /* Take the DUART out of reset */
96 titan_writel(0x00ff1cff, CPRR);
97
98#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
99 /* Enable both ports */
100 titan_writel(MASK_SER0 | MASK_SER1, UACFG);
101#else
102 /* Enable port #0 only */
103 titan_writel(MASK_SER0, UACFG);
104#endif
105
106 /*
107 * Set up serial port #0. Do not use autodetection; the result is
108 * not what we want.
109 */
110 memset(&up, 0, sizeof(up));
111 up.membase = (char *) titan_addr(REGBASE_SER0);
112 up.irq = TITAN_IRQ;
113 up.uartclk = TITAN_UART_CLK;
114 up.regshift = 0;
115 up.iotype = UPIO_RM9000;
116 up.type = PORT_RM9000;
117 up.flags = UPF_SHARE_IRQ;
118 up.line = 0;
119 if (early_serial_setup(&up))
120 printk(serr, up.line);
121
122#if CONFIG_SERIAL_8250_NR_UARTS > 1
123 /* And now for port #1. */
124 up.membase = (char *) titan_addr(REGBASE_SER1);
125 up.line = 1;
126 if (early_serial_setup(&up))
127 printk(serr, up.line);
128#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
129#else
130 /* Leave the DUART in reset */
131 titan_writel(0x00ff3cff, CPRR);
132#endif /* defined(CONFIG_SERIAL_8250) */
133
134 return 0;
135}
136
137static int __init excite_platform_init(void)
138{
139 unsigned int i;
140 unsigned char buf[3];
141 u8 reg;
142 void __iomem * dpr;
143
144 /* BIU buffer allocations */
145 ocd_writel(8, CPURSLMT); /* CPU */
146 titan_writel(4, CPGRWL); /* GPI / Ethernet */
147
148 /* Map control registers located in FPGA */
149 ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
150 if (!ctl_regs)
151 panic("eXcite: failed to map platform control registers\n");
152 memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
153 unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
154
155 /* Clear the reboot flag */
156 dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
157 reg = __raw_readb(dpr);
158 __raw_writeb(reg & 0x7f, dpr);
159 iounmap(dpr);
160
161 /* Interrupt controller setup */
162 for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
163 ocd_writel(0x00000000, i + 0x04);
164 ocd_writel(0xffffffff, i + 0x0c);
165 }
166 ocd_writel(0x2, NMICONFIG);
167
168 ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
169 INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
170 ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
171 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
172 INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
173 ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
174 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
175 INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
176 ocd_writel((0x1 << (PHY_MSGINT % 0x20))
177 | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
178 INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
179#if USB_IRQ < 10
180 ocd_writel((0x1 << (USB_MSGINT % 0x20))
181 | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
182 INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
183#endif
184 /* Enable the packet FIFO, XDMA and XDMA arbiter */
185 titan_writel(0x00ff18ff, CPRR);
186
187 /*
188 * Set up the PADMUX. Power down all ethernet slices,
189 * they will be powered up and configured at device startup.
190 */
191 titan_writel(0x00878206, CPTC1R);
192 titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
193
194 /* Reset and enable the FIFO block */
195 titan_writel(0x00000001, SDRXFCIE);
196 titan_writel(0x00000001, SDTXFCIE);
197 titan_writel(0x00000100, SDRXFCIE);
198 titan_writel(0x00000000, SDTXFCIE);
199
200 /*
201 * Initialize the common interrupt shared by all components of
202 * the GPI/Ethernet subsystem.
203 */
204 titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
205 titan_writel(TITAN_MSGINT, CPCFG1);
206
207 /*
208 * XDMA configuration.
209 * In order for the XDMA to be sharable among multiple drivers,
210 * the setup must be done here in the platform. The reason is that
211 * this setup can only be done while the XDMA is in reset. If this
212 * were done in a driver, it would interrupt all other drivers
213 * using the XDMA.
214 */
215 titan_writel(0x80021dff, GXCFG); /* XDMA reset */
216 titan_writel(0x00000000, CPXCISRA);
217 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
218#if defined(CONFIG_HIGHMEM)
219# error change for HIGHMEM support!
220#else
221 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
222#endif
223 titan_writel(0, GXDMA_DESCADR);
224
225 for (i = 0x5040; i <= 0x5300; i += 0x0040)
226 titan_writel(0x80080000, i); /* reset channel */
227
228 titan_writel((0x1 << 29) /* no sparse tx descr. */
229 | (0x1 << 28) /* no sparse rx descr. */
230 | (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
231 | (0x1 << 21) | (0x1 << 22) /* data coherency */
232 | (0x1 << 17)
233 | 0x1dff,
234 GXCFG);
235
236#if defined(CONFIG_SMP)
237# error No SMP support
238#else
239 /* All interrupts go to core #0 only. */
240 titan_writel(0x1f007fff, CPDST0A);
241 titan_writel(0x00000000, CPDST0B);
242 titan_writel(0x0000ff3f, CPDST1A);
243 titan_writel(0x00000000, CPDST1B);
244 titan_writel(0x00ffffff, CPXDSTA);
245 titan_writel(0x00000000, CPXDSTB);
246#endif
247
248 /* Enable DUART interrupts, disable everything else. */
249 titan_writel(0x04000000, CPGIG0ER);
250 titan_writel(0x000000c0, CPGIG1ER);
251
252 excite_procfs_init();
253 return 0;
254}
255
256void __init plat_mem_setup(void)
257{
258 volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
259
260 /* Announce RAM to system */
261 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
262
263 /* Set up the peripheral address map */
264 *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
265 *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
266 *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
267 *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
268 wmb();
269 *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
270 wmb();
271
272 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
273 ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
274 ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
275 ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
276
277 /* Local bus slot #0 */
278 ocd_writel(0x00040510, LDP0);
279 ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
280 ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
281
282 /* Local bus slot #2 */
283 ocd_writel(0x00000330, LDP2);
284 ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
285 ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
286
287 /* Local bus slot #3 */
288 ocd_writel(0x00123413, LDP3);
289 ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
290 ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
291}
292
293
294
295console_initcall(excite_init_console);
296arch_initcall(excite_platform_init);
297
298EXPORT_SYMBOL(titan_lock);
299EXPORT_SYMBOL(titan_irqflags);
300EXPORT_SYMBOL(titan_irq);
301EXPORT_SYMBOL(ocd_base);
302EXPORT_SYMBOL(titan_base);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 05:34:53 -0500