diff options
Diffstat (limited to 'arch/mips/au1000')
-rw-r--r-- | arch/mips/au1000/common/irq.c | 20 | ||||
-rw-r--r-- | arch/mips/au1000/pb1200/irqmap.c | 2 |
2 files changed, 11 insertions, 11 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index afe05ec12c27..da74ac21954b 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c | |||
@@ -333,31 +333,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) | |||
333 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | 333 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); |
334 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); | 334 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); |
335 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); | 335 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); |
336 | irq_desc[irq_nr].handler = &rise_edge_irq_type; | 336 | irq_desc[irq_nr].chip = &rise_edge_irq_type; |
337 | break; | 337 | break; |
338 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ | 338 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ |
339 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | 339 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); |
340 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); | 340 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); |
341 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | 341 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); |
342 | irq_desc[irq_nr].handler = &fall_edge_irq_type; | 342 | irq_desc[irq_nr].chip = &fall_edge_irq_type; |
343 | break; | 343 | break; |
344 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ | 344 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ |
345 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); | 345 | au_writel(1<<(irq_nr-32), IC1_CFG2CLR); |
346 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); | 346 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); |
347 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); | 347 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); |
348 | irq_desc[irq_nr].handler = &either_edge_irq_type; | 348 | irq_desc[irq_nr].chip = &either_edge_irq_type; |
349 | break; | 349 | break; |
350 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ | 350 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ |
351 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); | 351 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); |
352 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); | 352 | au_writel(1<<(irq_nr-32), IC1_CFG1CLR); |
353 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); | 353 | au_writel(1<<(irq_nr-32), IC1_CFG0SET); |
354 | irq_desc[irq_nr].handler = &level_irq_type; | 354 | irq_desc[irq_nr].chip = &level_irq_type; |
355 | break; | 355 | break; |
356 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ | 356 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ |
357 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); | 357 | au_writel(1<<(irq_nr-32), IC1_CFG2SET); |
358 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); | 358 | au_writel(1<<(irq_nr-32), IC1_CFG1SET); |
359 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | 359 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); |
360 | irq_desc[irq_nr].handler = &level_irq_type; | 360 | irq_desc[irq_nr].chip = &level_irq_type; |
361 | break; | 361 | break; |
362 | case INTC_INT_DISABLED: /* 0:0:0 */ | 362 | case INTC_INT_DISABLED: /* 0:0:0 */ |
363 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); | 363 | au_writel(1<<(irq_nr-32), IC1_CFG0CLR); |
@@ -385,31 +385,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) | |||
385 | au_writel(1<<irq_nr, IC0_CFG2CLR); | 385 | au_writel(1<<irq_nr, IC0_CFG2CLR); |
386 | au_writel(1<<irq_nr, IC0_CFG1CLR); | 386 | au_writel(1<<irq_nr, IC0_CFG1CLR); |
387 | au_writel(1<<irq_nr, IC0_CFG0SET); | 387 | au_writel(1<<irq_nr, IC0_CFG0SET); |
388 | irq_desc[irq_nr].handler = &rise_edge_irq_type; | 388 | irq_desc[irq_nr].chip = &rise_edge_irq_type; |
389 | break; | 389 | break; |
390 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ | 390 | case INTC_INT_FALL_EDGE: /* 0:1:0 */ |
391 | au_writel(1<<irq_nr, IC0_CFG2CLR); | 391 | au_writel(1<<irq_nr, IC0_CFG2CLR); |
392 | au_writel(1<<irq_nr, IC0_CFG1SET); | 392 | au_writel(1<<irq_nr, IC0_CFG1SET); |
393 | au_writel(1<<irq_nr, IC0_CFG0CLR); | 393 | au_writel(1<<irq_nr, IC0_CFG0CLR); |
394 | irq_desc[irq_nr].handler = &fall_edge_irq_type; | 394 | irq_desc[irq_nr].chip = &fall_edge_irq_type; |
395 | break; | 395 | break; |
396 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ | 396 | case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ |
397 | au_writel(1<<irq_nr, IC0_CFG2CLR); | 397 | au_writel(1<<irq_nr, IC0_CFG2CLR); |
398 | au_writel(1<<irq_nr, IC0_CFG1SET); | 398 | au_writel(1<<irq_nr, IC0_CFG1SET); |
399 | au_writel(1<<irq_nr, IC0_CFG0SET); | 399 | au_writel(1<<irq_nr, IC0_CFG0SET); |
400 | irq_desc[irq_nr].handler = &either_edge_irq_type; | 400 | irq_desc[irq_nr].chip = &either_edge_irq_type; |
401 | break; | 401 | break; |
402 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ | 402 | case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ |
403 | au_writel(1<<irq_nr, IC0_CFG2SET); | 403 | au_writel(1<<irq_nr, IC0_CFG2SET); |
404 | au_writel(1<<irq_nr, IC0_CFG1CLR); | 404 | au_writel(1<<irq_nr, IC0_CFG1CLR); |
405 | au_writel(1<<irq_nr, IC0_CFG0SET); | 405 | au_writel(1<<irq_nr, IC0_CFG0SET); |
406 | irq_desc[irq_nr].handler = &level_irq_type; | 406 | irq_desc[irq_nr].chip = &level_irq_type; |
407 | break; | 407 | break; |
408 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ | 408 | case INTC_INT_LOW_LEVEL: /* 1:1:0 */ |
409 | au_writel(1<<irq_nr, IC0_CFG2SET); | 409 | au_writel(1<<irq_nr, IC0_CFG2SET); |
410 | au_writel(1<<irq_nr, IC0_CFG1SET); | 410 | au_writel(1<<irq_nr, IC0_CFG1SET); |
411 | au_writel(1<<irq_nr, IC0_CFG0CLR); | 411 | au_writel(1<<irq_nr, IC0_CFG0CLR); |
412 | irq_desc[irq_nr].handler = &level_irq_type; | 412 | irq_desc[irq_nr].chip = &level_irq_type; |
413 | break; | 413 | break; |
414 | case INTC_INT_DISABLED: /* 0:0:0 */ | 414 | case INTC_INT_DISABLED: /* 0:0:0 */ |
415 | au_writel(1<<irq_nr, IC0_CFG0CLR); | 415 | au_writel(1<<irq_nr, IC0_CFG0CLR); |
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c index bacc0c6bfe67..5dd164fc1889 100644 --- a/arch/mips/au1000/pb1200/irqmap.c +++ b/arch/mips/au1000/pb1200/irqmap.c | |||
@@ -172,7 +172,7 @@ void _board_init_irq(void) | |||
172 | 172 | ||
173 | for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++) | 173 | for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++) |
174 | { | 174 | { |
175 | irq_desc[irq_nr].handler = &external_irq_type; | 175 | irq_desc[irq_nr].chip = &external_irq_type; |
176 | pb1200_disable_irq(irq_nr); | 176 | pb1200_disable_irq(irq_nr); |
177 | } | 177 | } |
178 | 178 | ||