diff options
Diffstat (limited to 'arch/mips/au1000/pb1200/board_setup.c')
-rw-r--r-- | arch/mips/au1000/pb1200/board_setup.c | 139 |
1 files changed, 66 insertions, 73 deletions
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c index 4493a792cc4c..6cb2115059ad 100644 --- a/arch/mips/au1000/pb1200/board_setup.c +++ b/arch/mips/au1000/pb1200/board_setup.c | |||
@@ -27,16 +27,8 @@ | |||
27 | #include <linux/init.h> | 27 | #include <linux/init.h> |
28 | #include <linux/sched.h> | 28 | #include <linux/sched.h> |
29 | 29 | ||
30 | #include <au1000.h> | ||
31 | #include <prom.h> | 30 | #include <prom.h> |
32 | 31 | #include <au1xxx.h> | |
33 | #ifdef CONFIG_MIPS_PB1200 | ||
34 | #include <asm/mach-pb1x00/pb1200.h> | ||
35 | #endif | ||
36 | |||
37 | #ifdef CONFIG_MIPS_DB1200 | ||
38 | #include <asm/mach-db1x00/db1200.h> | ||
39 | #endif | ||
40 | 32 | ||
41 | extern void _board_init_irq(void); | 33 | extern void _board_init_irq(void); |
42 | extern void (*board_init_irq)(void); | 34 | extern void (*board_init_irq)(void); |
@@ -53,56 +45,57 @@ void __init board_setup(void) | |||
53 | 45 | ||
54 | #if 0 | 46 | #if 0 |
55 | { | 47 | { |
56 | u32 pin_func; | 48 | u32 pin_func; |
57 | 49 | ||
58 | /* Enable PSC1 SYNC for AC97. Normaly done in audio driver, | 50 | /* |
59 | * but it is board specific code, so put it here. | 51 | * Enable PSC1 SYNC for AC97. Normaly done in audio driver, |
60 | */ | 52 | * but it is board specific code, so put it here. |
61 | pin_func = au_readl(SYS_PINFUNC); | 53 | */ |
62 | au_sync(); | 54 | pin_func = au_readl(SYS_PINFUNC); |
63 | pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; | 55 | au_sync(); |
64 | au_writel(pin_func, SYS_PINFUNC); | 56 | pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; |
65 | 57 | au_writel(pin_func, SYS_PINFUNC); | |
66 | au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */ | 58 | |
67 | au_sync(); | 59 | au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ |
60 | au_sync(); | ||
68 | } | 61 | } |
69 | #endif | 62 | #endif |
70 | 63 | ||
71 | #if defined(CONFIG_I2C_AU1550) | 64 | #if defined(CONFIG_I2C_AU1550) |
72 | { | 65 | { |
73 | u32 freq0, clksrc; | 66 | u32 freq0, clksrc; |
74 | u32 pin_func; | 67 | u32 pin_func; |
75 | 68 | ||
76 | /* Select SMBUS in CPLD */ | 69 | /* Select SMBus in CPLD */ |
77 | bcsr->resets &= ~(BCSR_RESETS_PCS0MUX); | 70 | bcsr->resets &= ~BCSR_RESETS_PCS0MUX; |
78 | 71 | ||
79 | pin_func = au_readl(SYS_PINFUNC); | 72 | pin_func = au_readl(SYS_PINFUNC); |
80 | au_sync(); | 73 | au_sync(); |
81 | pin_func &= ~(3<<17 | 1<<4); | 74 | pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); |
82 | /* Set GPIOs correctly */ | 75 | /* Set GPIOs correctly */ |
83 | pin_func |= 2<<17; | 76 | pin_func |= 2 << 17; |
84 | au_writel(pin_func, SYS_PINFUNC); | 77 | au_writel(pin_func, SYS_PINFUNC); |
85 | au_sync(); | 78 | au_sync(); |
86 | 79 | ||
87 | /* The i2c driver depends on 50Mhz clock */ | 80 | /* The I2C driver depends on 50 MHz clock */ |
88 | freq0 = au_readl(SYS_FREQCTRL0); | 81 | freq0 = au_readl(SYS_FREQCTRL0); |
89 | au_sync(); | 82 | au_sync(); |
90 | freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); | 83 | freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); |
91 | freq0 |= (3<<SYS_FC_FRDIV1_BIT); | 84 | freq0 |= 3 << SYS_FC_FRDIV1_BIT; |
92 | /* 396Mhz / (3+1)*2 == 49.5Mhz */ | 85 | /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */ |
93 | au_writel(freq0, SYS_FREQCTRL0); | 86 | au_writel(freq0, SYS_FREQCTRL0); |
94 | au_sync(); | 87 | au_sync(); |
95 | freq0 |= SYS_FC_FE1; | 88 | freq0 |= SYS_FC_FE1; |
96 | au_writel(freq0, SYS_FREQCTRL0); | 89 | au_writel(freq0, SYS_FREQCTRL0); |
97 | au_sync(); | 90 | au_sync(); |
98 | 91 | ||
99 | clksrc = au_readl(SYS_CLKSRC); | 92 | clksrc = au_readl(SYS_CLKSRC); |
100 | au_sync(); | 93 | au_sync(); |
101 | clksrc &= ~0x01f00000; | 94 | clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK); |
102 | /* bit 22 is EXTCLK0 for PSC0 */ | 95 | /* Bit 22 is EXTCLK0 for PSC0 */ |
103 | clksrc |= (0x3 << 22); | 96 | clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT; |
104 | au_writel(clksrc, SYS_CLKSRC); | 97 | au_writel(clksrc, SYS_CLKSRC); |
105 | au_sync(); | 98 | au_sync(); |
106 | } | 99 | } |
107 | #endif | 100 | #endif |
108 | 101 | ||
@@ -116,27 +109,27 @@ void __init board_setup(void) | |||
116 | #endif | 109 | #endif |
117 | #endif | 110 | #endif |
118 | 111 | ||
119 | /* The Pb1200 development board uses external MUX for PSC0 to | 112 | /* |
120 | support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI | 113 | * The Pb1200 development board uses external MUX for PSC0 to |
121 | */ | 114 | * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI |
115 | */ | ||
122 | #ifdef CONFIG_I2C_AU1550 | 116 | #ifdef CONFIG_I2C_AU1550 |
123 | bcsr->resets &= (~BCSR_RESETS_PCS0MUX); | 117 | bcsr->resets &= ~BCSR_RESETS_PCS0MUX; |
124 | #endif | 118 | #endif |
125 | au_sync(); | 119 | au_sync(); |
126 | 120 | ||
127 | #ifdef CONFIG_MIPS_PB1200 | 121 | #ifdef CONFIG_MIPS_PB1200 |
128 | printk("AMD Alchemy Pb1200 Board\n"); | 122 | printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); |
129 | #endif | 123 | #endif |
130 | #ifdef CONFIG_MIPS_DB1200 | 124 | #ifdef CONFIG_MIPS_DB1200 |
131 | printk("AMD Alchemy Db1200 Board\n"); | 125 | printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); |
132 | #endif | 126 | #endif |
133 | 127 | ||
134 | /* Setup Pb1200 External Interrupt Controller */ | 128 | /* Setup Pb1200 External Interrupt Controller */ |
135 | board_init_irq = _board_init_irq; | 129 | board_init_irq = _board_init_irq; |
136 | } | 130 | } |
137 | 131 | ||
138 | int | 132 | int board_au1200fb_panel(void) |
139 | board_au1200fb_panel(void) | ||
140 | { | 133 | { |
141 | BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; | 134 | BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
142 | int p; | 135 | int p; |
@@ -147,23 +140,23 @@ board_au1200fb_panel(void) | |||
147 | return p; | 140 | return p; |
148 | } | 141 | } |
149 | 142 | ||
150 | int | 143 | int board_au1200fb_panel_init(void) |
151 | board_au1200fb_panel_init(void) | ||
152 | { | 144 | { |
153 | /* Apply power */ | 145 | /* Apply power */ |
154 | BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; | 146 | BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
155 | bcsr->board |= (BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); | 147 | |
156 | /*printk("board_au1200fb_panel_init()\n"); */ | 148 | bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL; |
149 | /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */ | ||
157 | return 0; | 150 | return 0; |
158 | } | 151 | } |
159 | 152 | ||
160 | int | 153 | int board_au1200fb_panel_shutdown(void) |
161 | board_au1200fb_panel_shutdown(void) | ||
162 | { | 154 | { |
163 | /* Remove power */ | 155 | /* Remove power */ |
164 | BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; | 156 | BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
165 | bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); | 157 | |
166 | /*printk("board_au1200fb_panel_shutdown()\n"); */ | 158 | bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | |
159 | BCSR_BOARD_LCDBL); | ||
160 | /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */ | ||
167 | return 0; | 161 | return 0; |
168 | } | 162 | } |
169 | |||