1 files changed, 57 insertions, 60 deletions

diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c
index 33f15acc1b17..25df167a95b3 100644
--- a/arch/mips/au1000/pb1000/board_setup.c
+++ b/arch/mips/au1000/pb1000/board_setup.c
@@ -1,7 +1,6 @@
 /*
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
@@ -40,128 +39,126 @@ void __init board_setup(void)
         u32 sys_freqctrl, sys_clksrc;
         u32 prid = read_c0_prid();
 
-        // set AUX clock to 12MHz * 8 = 96 MHz
+        /* Set AUX clock to 12 MHz * 8 = 96 MHz */
         au_writel(8, SYS_AUXPLL);
         au_writel(0, SYS_PINSTATERD);
         udelay(100);
 
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-        /* zero and disable FREQ2 */
+        /* Zero and disable FREQ2 */
         sys_freqctrl = au_readl(SYS_FREQCTRL0);
         sys_freqctrl &= ~0xFFF00000;
         au_writel(sys_freqctrl, SYS_FREQCTRL0);
 
-        /* zero and disable USBH/USBD clocks */
+        /* Zero and disable USBH/USBD clocks */
         sys_clksrc = au_readl(SYS_CLKSRC);
-        sys_clksrc &= ~0x00007FE0;
+        sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
+                        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
         au_writel(sys_clksrc, SYS_CLKSRC);
 
         sys_freqctrl = au_readl(SYS_FREQCTRL0);
         sys_freqctrl &= ~0xFFF00000;
 
         sys_clksrc = au_readl(SYS_CLKSRC);
-        sys_clksrc &= ~0x00007FE0;
+        sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
+                        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
 
-        switch (prid & 0x000000FF)
-        {
+        switch (prid & 0x000000FF) {
         case 0x00: /* DA */
         case 0x01: /* HA */
         case 0x02: /* HB */
-        /* CPU core freq to 48MHz to slow it way down... */
-        au_writel(4, SYS_CPUPLL);
+                /* CPU core freq to 48 MHz to slow it way down... */
+                au_writel(4, SYS_CPUPLL);
 
-        /*
-         * Setup 48MHz FREQ2 from CPUPLL for USB Host
-         */
-        /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
-        sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
-        au_writel(sys_freqctrl, SYS_FREQCTRL0);
+                /*
+                 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
+                 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
+                 */
+                sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
+                au_writel(sys_freqctrl, SYS_FREQCTRL0);
 
-        /* CPU core freq to 384MHz */
-        au_writel(0x20, SYS_CPUPLL);
+                /* CPU core freq to 384 MHz */
+                au_writel(0x20, SYS_CPUPLL);
 
-        printk("Au1000: 48MHz OHCI workaround enabled\n");
+                printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
                 break;
 
-        default:  /* HC and newer */
-        // FREQ2 = aux/2 = 48 MHz
-        sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
-        au_writel(sys_freqctrl, SYS_FREQCTRL0);
+        default: /* HC and newer */
+                /* FREQ2 = aux / 2 = 48 MHz */
+                sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
+                                 SYS_FC_FE2 | SYS_FC_FS2;
+                au_writel(sys_freqctrl, SYS_FREQCTRL0);
                 break;
         }
 
         /*
-         * Route 48MHz FREQ2 into USB Host and/or Device
+         * Route 48 MHz FREQ2 into USB Host and/or Device
          */
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-        sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
-#endif
+        sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
         au_writel(sys_clksrc, SYS_CLKSRC);
 
-        // configure pins GPIO[14:9] as GPIO
-        pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
+        /* Configure pins GPIO[14:9] as GPIO */
+        pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
 
-        // 2nd USB port is USB host
-        pin_func |= 0x8000;
+        /* 2nd USB port is USB host */
+        pin_func |= SYS_PF_USB;
 
         au_writel(pin_func, SYS_PINFUNC);
         au_writel(0x2800, SYS_TRIOUTCLR);
         au_writel(0x0030, SYS_OUTPUTCLR);
 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 
-        // make gpio 15 an input (for interrupt line)
-        pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
-        // we don't need I2S, so make it available for GPIO[31:29]
-        pin_func |= (1<<5);
+        /* Make GPIO 15 an input (for interrupt line) */
+        pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
+        /* We don't need I2S, so make it available for GPIO[31:29] */
+        pin_func |= SYS_PF_I2S;
         au_writel(pin_func, SYS_PINFUNC);
 
         au_writel(0x8000, SYS_TRIOUTCLR);
 
-        static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
+        static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
         au_writel(static_cfg0, MEM_STCFG0);
 
-        // configure RCE2* for LCD
+        /* configure RCE2* for LCD */
         au_writel(0x00000004, MEM_STCFG2);
 
-        // MEM_STTIME2
+        /* MEM_STTIME2 */
         au_writel(0x09000000, MEM_STTIME2);
 
-        // Set 32-bit base address decoding for RCE2*
+        /* Set 32-bit base address decoding for RCE2* */
         au_writel(0x10003ff0, MEM_STADDR2);
 
-        // PCI CPLD setup
-        // expand CE0 to cover PCI
+        /*
+         * PCI CPLD setup
+         * Expand CE0 to cover PCI
+         */
         au_writel(0x11803e40, MEM_STADDR1);
 
-        // burst visibility on
+        /* Burst visibility on */
         au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
 
-        au_writel(0x83, MEM_STCFG1);         // ewait enabled, flash timing
-        au_writel(0x33030a10, MEM_STTIME1);   // slower timing for FPGA
+        au_writel(0x83, MEM_STCFG1);         /* ewait enabled, flash timing */
+        au_writel(0x33030a10, MEM_STTIME1);  /* slower timing for FPGA */
 
-        /* setup the static bus controller */
+        /* Setup the static bus controller */
         au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
         au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
         au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
 
-#ifdef CONFIG_PCI
-        au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
-        au_writel(0, SDRAM_MBAR);        // set mbar to 0
-        au_writel(0x2, SDRAM_CMD);       // enable memory accesses
-        au_sync_delay(1);
-#endif
-
-        /* Enable Au1000 BCLK switching - note: sed1356 must not use
-         * its BCLK (Au1000 LCLK) for any timings */
-        switch (prid & 0x000000FF)
-        {
+        /*
+         * Enable Au1000 BCLK switching - note: sed1356 must not use
+         * its BCLK (Au1000 LCLK) for any timings
+         */
+        switch (prid & 0x000000FF) {
         case 0x00: /* DA */
         case 0x01: /* HA */
         case 0x02: /* HB */
                 break;
         default:  /* HC and newer */
-                /* Enable sys bus clock divider when IDLE state or no bus
-                   activity. */
+                /*
+                 * Enable sys bus clock divider when IDLE state or no bus
+                 * activity.
+                 */
                 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
                 break;
         }