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-rw-r--r--arch/mips/au1000/common/irq.c63
-rw-r--r--arch/mips/au1000/common/pci.c8
2 files changed, 26 insertions, 45 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 2abe132bb07d..9cf7b6715836 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -70,7 +70,6 @@ extern irq_cpustat_t irq_stat [NR_CPUS];
70extern void mips_timer_interrupt(void); 70extern void mips_timer_interrupt(void);
71 71
72static void setup_local_irq(unsigned int irq, int type, int int_req); 72static void setup_local_irq(unsigned int irq, int type, int int_req);
73static unsigned int startup_irq(unsigned int irq);
74static void end_irq(unsigned int irq_nr); 73static void end_irq(unsigned int irq_nr);
75static inline void mask_and_ack_level_irq(unsigned int irq_nr); 74static inline void mask_and_ack_level_irq(unsigned int irq_nr);
76static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); 75static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
@@ -84,20 +83,6 @@ void (*board_init_irq)(void);
84static DEFINE_SPINLOCK(irq_lock); 83static DEFINE_SPINLOCK(irq_lock);
85 84
86 85
87static unsigned int startup_irq(unsigned int irq_nr)
88{
89 local_enable_irq(irq_nr);
90 return 0;
91}
92
93
94static void shutdown_irq(unsigned int irq_nr)
95{
96 local_disable_irq(irq_nr);
97 return;
98}
99
100
101inline void local_enable_irq(unsigned int irq_nr) 86inline void local_enable_irq(unsigned int irq_nr)
102{ 87{
103 if (irq_nr > AU1000_LAST_INTC0_INT) { 88 if (irq_nr > AU1000_LAST_INTC0_INT) {
@@ -249,41 +234,37 @@ void restore_local_and_enable(int controller, unsigned long mask)
249 234
250static struct irq_chip rise_edge_irq_type = { 235static struct irq_chip rise_edge_irq_type = {
251 .typename = "Au1000 Rise Edge", 236 .typename = "Au1000 Rise Edge",
252 .startup = startup_irq,
253 .shutdown = shutdown_irq,
254 .enable = local_enable_irq,
255 .disable = local_disable_irq,
256 .ack = mask_and_ack_rise_edge_irq, 237 .ack = mask_and_ack_rise_edge_irq,
238 .mask = local_disable_irq,
239 .mask_ack = mask_and_ack_rise_edge_irq,
240 .unmask = local_enable_irq,
257 .end = end_irq, 241 .end = end_irq,
258}; 242};
259 243
260static struct irq_chip fall_edge_irq_type = { 244static struct irq_chip fall_edge_irq_type = {
261 .typename = "Au1000 Fall Edge", 245 .typename = "Au1000 Fall Edge",
262 .startup = startup_irq,
263 .shutdown = shutdown_irq,
264 .enable = local_enable_irq,
265 .disable = local_disable_irq,
266 .ack = mask_and_ack_fall_edge_irq, 246 .ack = mask_and_ack_fall_edge_irq,
247 .mask = local_disable_irq,
248 .mask_ack = mask_and_ack_fall_edge_irq,
249 .unmask = local_enable_irq,
267 .end = end_irq, 250 .end = end_irq,
268}; 251};
269 252
270static struct irq_chip either_edge_irq_type = { 253static struct irq_chip either_edge_irq_type = {
271 .typename = "Au1000 Rise or Fall Edge", 254 .typename = "Au1000 Rise or Fall Edge",
272 .startup = startup_irq,
273 .shutdown = shutdown_irq,
274 .enable = local_enable_irq,
275 .disable = local_disable_irq,
276 .ack = mask_and_ack_either_edge_irq, 255 .ack = mask_and_ack_either_edge_irq,
256 .mask = local_disable_irq,
257 .mask_ack = mask_and_ack_either_edge_irq,
258 .unmask = local_enable_irq,
277 .end = end_irq, 259 .end = end_irq,
278}; 260};
279 261
280static struct irq_chip level_irq_type = { 262static struct irq_chip level_irq_type = {
281 .typename = "Au1000 Level", 263 .typename = "Au1000 Level",
282 .startup = startup_irq,
283 .shutdown = shutdown_irq,
284 .enable = local_enable_irq,
285 .disable = local_disable_irq,
286 .ack = mask_and_ack_level_irq, 264 .ack = mask_and_ack_level_irq,
265 .mask = local_disable_irq,
266 .mask_ack = mask_and_ack_level_irq,
267 .unmask = local_enable_irq,
287 .end = end_irq, 268 .end = end_irq,
288}; 269};
289 270
@@ -328,31 +309,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
328 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 309 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
329 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 310 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
330 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 311 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
331 irq_desc[irq_nr].chip = &rise_edge_irq_type; 312 set_irq_chip(irq_nr, &rise_edge_irq_type);
332 break; 313 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 314 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 315 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
335 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 316 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
336 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 317 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
337 irq_desc[irq_nr].chip = &fall_edge_irq_type; 318 set_irq_chip(irq_nr, &fall_edge_irq_type);
338 break; 319 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 320 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 321 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
341 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 322 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
342 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 323 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
343 irq_desc[irq_nr].chip = &either_edge_irq_type; 324 set_irq_chip(irq_nr, &either_edge_irq_type);
344 break; 325 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 326 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 327 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
347 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 328 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
348 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 329 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
349 irq_desc[irq_nr].chip = &level_irq_type; 330 set_irq_chip(irq_nr, &level_irq_type);
350 break; 331 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 332 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 333 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
353 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 334 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
354 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 335 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
355 irq_desc[irq_nr].chip = &level_irq_type; 336 set_irq_chip(irq_nr, &level_irq_type);
356 break; 337 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */ 338 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 339 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
@@ -380,31 +361,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
380 au_writel(1<<irq_nr, IC0_CFG2CLR); 361 au_writel(1<<irq_nr, IC0_CFG2CLR);
381 au_writel(1<<irq_nr, IC0_CFG1CLR); 362 au_writel(1<<irq_nr, IC0_CFG1CLR);
382 au_writel(1<<irq_nr, IC0_CFG0SET); 363 au_writel(1<<irq_nr, IC0_CFG0SET);
383 irq_desc[irq_nr].chip = &rise_edge_irq_type; 364 set_irq_chip(irq_nr, &rise_edge_irq_type);
384 break; 365 break;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 366 case INTC_INT_FALL_EDGE: /* 0:1:0 */
386 au_writel(1<<irq_nr, IC0_CFG2CLR); 367 au_writel(1<<irq_nr, IC0_CFG2CLR);
387 au_writel(1<<irq_nr, IC0_CFG1SET); 368 au_writel(1<<irq_nr, IC0_CFG1SET);
388 au_writel(1<<irq_nr, IC0_CFG0CLR); 369 au_writel(1<<irq_nr, IC0_CFG0CLR);
389 irq_desc[irq_nr].chip = &fall_edge_irq_type; 370 set_irq_chip(irq_nr, &fall_edge_irq_type);
390 break; 371 break;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 372 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
392 au_writel(1<<irq_nr, IC0_CFG2CLR); 373 au_writel(1<<irq_nr, IC0_CFG2CLR);
393 au_writel(1<<irq_nr, IC0_CFG1SET); 374 au_writel(1<<irq_nr, IC0_CFG1SET);
394 au_writel(1<<irq_nr, IC0_CFG0SET); 375 au_writel(1<<irq_nr, IC0_CFG0SET);
395 irq_desc[irq_nr].chip = &either_edge_irq_type; 376 set_irq_chip(irq_nr, &either_edge_irq_type);
396 break; 377 break;
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 378 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
398 au_writel(1<<irq_nr, IC0_CFG2SET); 379 au_writel(1<<irq_nr, IC0_CFG2SET);
399 au_writel(1<<irq_nr, IC0_CFG1CLR); 380 au_writel(1<<irq_nr, IC0_CFG1CLR);
400 au_writel(1<<irq_nr, IC0_CFG0SET); 381 au_writel(1<<irq_nr, IC0_CFG0SET);
401 irq_desc[irq_nr].chip = &level_irq_type; 382 set_irq_chip(irq_nr, &level_irq_type);
402 break; 383 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 384 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
404 au_writel(1<<irq_nr, IC0_CFG2SET); 385 au_writel(1<<irq_nr, IC0_CFG2SET);
405 au_writel(1<<irq_nr, IC0_CFG1SET); 386 au_writel(1<<irq_nr, IC0_CFG1SET);
406 au_writel(1<<irq_nr, IC0_CFG0CLR); 387 au_writel(1<<irq_nr, IC0_CFG0CLR);
407 irq_desc[irq_nr].chip = &level_irq_type; 388 set_irq_chip(irq_nr, &level_irq_type);
408 break; 389 break;
409 case INTC_INT_DISABLED: /* 0:0:0 */ 390 case INTC_INT_DISABLED: /* 0:0:0 */
410 au_writel(1<<irq_nr, IC0_CFG0CLR); 391 au_writel(1<<irq_nr, IC0_CFG0CLR);
diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c
index da591f674893..9f8ce08e173b 100644
--- a/arch/mips/au1000/common/pci.c
+++ b/arch/mips/au1000/common/pci.c
@@ -39,15 +39,15 @@
39 39
40/* TBD */ 40/* TBD */
41static struct resource pci_io_resource = { 41static struct resource pci_io_resource = {
42 .start = PCI_IO_START, 42 .start = (resource_size_t)PCI_IO_START,
43 .end = PCI_IO_END, 43 .end = (resource_size_t)PCI_IO_END,
44 .name = "PCI IO space", 44 .name = "PCI IO space",
45 .flags = IORESOURCE_IO 45 .flags = IORESOURCE_IO
46}; 46};
47 47
48static struct resource pci_mem_resource = { 48static struct resource pci_mem_resource = {
49 .start = PCI_MEM_START, 49 .start = (resource_size_t)PCI_MEM_START,
50 .end = PCI_MEM_END, 50 .end = (resource_size_t)PCI_MEM_END,
51 .name = "PCI memory space", 51 .name = "PCI memory space",
52 .flags = IORESOURCE_MEM 52 .flags = IORESOURCE_MEM
53}; 53};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 08:34:40 -0500